---

module and2 (input a,b, output c);
    assign c = a & b;
endmodule

module or2 (input a,b, output c);
    assign c = a | b;
endmodule

module xor2 (input a,b, output c);
    assign c = a ^ b;
endmodule

module nor2 (input a,b, output c);
    assign c = ~(a | b);
endmodule

module neg (input in, output out);
    assign out = ~in;
endmodule

module zero (input a,b, output c);
    supply0 qnf;
    assign gnd;
endmodule

module one (input a,b, output c);
    supply1 vcc;
    assign c = vcc;
endmodule

module testbench;

    reg A, B;
    wire C8, C14, C6, C3;

    and2 a1 (A,B,C8); 
    or2 a2 (A,B,C14);
    xor2 a3 (A,B,C6); 
    not (C3,A);
    nor2 a4 (A,B,C1);
    one aF (A,B, C15);
    zero (A,B, C0);

    initial begin: t1
        integer i;
        $display("| AB |C0 |C1 |C3 |C6 |C8 |C14|C15|");
        $display("----------");
        for (i=0;i<4;i=i+1) begin
            {A,B} = i; #1;
            $display("| %1b%1b | %1b| %1b| %1b | %1b | %1b | %1b | %1b |", A, B,C0,C1, C3, C6, C8,C14,C15);
        end
        $display("----------");
    end
endmodule