---

library ieee;
use ieee.std_logic_1164.all;

entity mode_display is
port (
    clk      : in std_logic;
    mode     : in std_logic;
    mode_seg : out std_logic_vector(7 downto 0)
);
end mode_display;

architecture rtl of mode_display is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if mode = '0' then
                mode_seg <= "11000111";  -- "L" для Logic
            else
                mode_seg <= "10100001";  -- "d" для DSP
            end if;
        end if;
    end process;
end rtl;