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Конфиг imx95
# SM configuration file for the MX95 EVK
MAKE soc=MIMX95, board=mcimx95evk, build=gcc_cross
DOX name=MX95EVK, desc="i.MX95 EVK Configuration Data"
include ../devices/MIMX95/configtool/device.cfg
#==========================================================================#
# Board #
#==========================================================================#
BOARD DEBUG_UART_INSTANCE=2
BOARD DEBUG_UART_BAUDRATE=115200
BOARD I2C_INSTANCE=1
BOARD I2C_BAUDRATE=400000
#==========================================================================#
# Common Defines #
#==========================================================================#
NOTIFY: api=notify
GET: api=get
SET: api=set
PRIV: api=priv
ALL: api=all
READONLY: perm=ro
#==========================================================================#
# ELE Domain #
#==========================================================================#
DOM0 name="ELE", did=0
OWNER: perm=sec_rw, api=all
ACCESS: perm=sec_rw, api=none, mdid=none
DATA: perm=rw
# Resources
# Sharing MP access may not be safe if FuSa SW using EDMA2
EDMA2_MP ACCESS
EDMA2_CH0_1 OWNER
V2X_ACC OWNER
# Memory
M33_TCM_SYS DATA, begin=0x020200000, size=256K
OCRAM DATA, begin=0x020480000, size=352K
DDR DATA, begin=0x080000000, end=0x87FFFFFFF, nodbg
#==========================================================================#
# ISP Domain #
#==========================================================================#
DOM10 name="ISP", did=10
OWNER: perm=rw
#==========================================================================#
# V2X Domain #
#==========================================================================#
DOM12 name="V2X", did=12
DFMT1: sa=bypass, pa=bypass
OWNER:
# Resources
V2X_FH OWNER
# Memory
DDR READONLY, begin=0x080000000, end=0x08AFFFFFF, nodbg
DDR DATA, begin=0x08B000000, end=0x08BFFFFFF, nodbg
DDR READONLY, begin=0x08C000000, end=0x87FFFFFFF, nodbg
#==========================================================================#
# SM M33 EENV #
#==========================================================================#
LM0 name="SM", rpc=none, boot=1, did=2, safe=feenv
DFMT0: sa=secure
DFMT1: sa=secure, pa=privileged
OWNER: perm=sec_rw, api=all
ACCESS: perm=sec_rw, api=none, mdid=none
TEST_MU: perm=sec_rw
EXEC: perm=sec_rwx
DATA: perm=sec_rw
MODE msel=1, boot=1
MODE msel=2, boot=1
# API
# SM CLocks
CLK_ADC ALL
CLK_FRO ALL
CLK_OSC24M ALL
CLK_OSC32K ALL
CLK_SYSPLL1_PFD0 ALL
CLK_SYSPLL1_PFD0_DIV2 ALL
CLK_SYSPLL1_PFD0_UNGATED ALL
CLK_SYSPLL1_PFD1 ALL
CLK_SYSPLL1_PFD1_DIV2 ALL
CLK_SYSPLL1_PFD1_UNGATED ALL
CLK_SYSPLL1_PFD2 ALL
CLK_SYSPLL1_PFD2_DIV2 ALL
CLK_SYSPLL1_PFD2_UNGATED ALL
CLK_SYSPLL1_VCO ALL
CLK_TEMPSENSE_GPR_SEL ALL
CLK_TMU ALL
# Modified via PERF protocol
CLK_A55 ALL
CLK_A55C0_GPR_SEL ALL
CLK_A55C1_GPR_SEL ALL
CLK_A55C2_GPR_SEL ALL
CLK_A55C3_GPR_SEL ALL
CLK_A55C4_GPR_SEL ALL
CLK_A55C5_GPR_SEL ALL
CLK_A55MTRBUS ALL
CLK_A55P_GPR_SEL ALL
CLK_A55PERIPH ALL
CLK_BUSAON ALL
CLK_BUSM7 ALL
CLK_BUSNETCMIX ALL
CLK_BUSWAKEUP ALL
CLK_CAMAPB ALL
CLK_CAMAXI ALL
CLK_CAMCM0 ALL
CLK_CAMISI ALL
CLK_DISPAPB ALL
CLK_DISPAXI ALL
CLK_DISPOCRAM ALL
CLK_DRAM_GPR_SEL ALL
CLK_DRAMALT ALL
CLK_DRAMAPB ALL
CLK_ELE ALL
CLK_ENET ALL
CLK_GPU ALL
CLK_GPUAPB ALL
CLK_HSIO ALL
CLK_M33 ALL
CLK_M7 ALL
CLK_NOC ALL
CLK_NOCAPB ALL
CLK_NPU ALL
CLK_NPUAPB ALL
CLK_V2XPK ALL
CLK_V2XPK ALL
CLK_VPU ALL
CLK_VPUAPB ALL
CLK_VPUJPEG ALL
CLK_WAKEUPAXI ALL
# Test CLocks
CLK_ENETPHYTEST200M ALL
CLK_ENETPHYTEST500M ALL
CLK_ENETPHYTEST667M ALL
CLK_HSIOACSCAN480M ALL
CLK_HSIOACSCAN80M ALL
CLK_HSIOPCIETEST160M ALL
CLK_HSIOPCIETEST400M ALL
CLK_HSIOPCIETEST500M ALL
CLK_HSIOUSBTEST50M ALL
CLK_HSIOUSBTEST60M ALL
# Resources
M33P OWNER # CPUs must be first
ANATOP OWNER
ATU_A OWNER
ATU_M OWNER
AXBS_AON OWNER
BBNSM OWNER
BLK_CTRL_BBSMMIX OWNER
BLK_CTRL_DDRMIX OWNER
BLK_CTRL_GPUMIX OWNER
BLK_CTRL_NOCMIX OWNER
BLK_CTRL_NS_AONMIX OWNER
BLK_CTRL_S_AONMIX OWNER
BLK_CTRL_WAKEUPMIX OWNER
CCM OWNER
DAP OWNER
DDR_CTRL OWNER
DDR_PHY OWNER
DDR_PM OWNER
DRAM_PLL OWNER
ELE OWNER
FSB READONLY
GIC ACCESS
GPC OWNER
GPIO1 OWNER
GPR0 OWNER
GPR1 OWNER
GPR2 OWNER
GPR3 OWNER
GPV_CAMERA OWNER
GPV_CENTRAL OWNER
GPV_DISPLAY OWNER
GPV_HSIO OWNER
GPV_MAIN OWNER
GPV_MEGA OWNER
GPV_VPU OWNER
IOMUXC OWNER
IOMUX_GPR OWNER
JTAG OWNER
LPI2C1 OWNER
LPUART2 OWNER
M33_CACHE_CTRL OWNER
M33_PCF OWNER
M33_PSF OWNER
M33_TCM_ECC OWNER
MU1_A TEST_MU
MU1_B OWNER
MU2_A TEST_MU
MU2_B OWNER
MU3_A TEST_MU
MU3_B OWNER
MU4_A TEST_MU
MU4_B OWNER
MU5_A TEST_MU
MU5_B OWNER
MU6_A TEST_MU
MU6_B OWNER
MU_ELE0 OWNER
ROMCP_M33 OWNER
SRAM_CTL_1 OWNER
SRAM_CTL_N OWNER
SRC OWNER
SYSCTR_CTL OWNER
SYSCTR_RD OWNER
TEMP_A55 OWNER
TRDC_A OWNER
TRDC_C OWNER
TRDC_D OWNER
TRDC_E OWNER
TRDC_G OWNER
TRDC_H OWNER
TRDC_M OWNER
TRDC_N OWNER
TRDC_V OWNER
TRDC_W OWNER
TSTMR1 OWNER
WDOG1 OWNER
WDOG2 OWNER
# SAF
CMU_A1 OWNER
CMU_A2 OWNER
CMU_ANA OWNER
CMU_DDR1 OWNER
CMU_DDR2 OWNER
CMU_N1 OWNER
CMU_N2 OWNER
CMU_W1 OWNER
CMU_W2 OWNER
CRC_A OWNER
C_STCU OWNER
DMA_CRC OWNER
EIM_A OWNER
EIM_N OWNER
EIM_NPU OWNER
EIM_W OWNER
ERM_A OWNER
ERM_NPU OWNER
ERM_W OWNER
FCCU OWNER
FCCU_FHID OWNER
INTM OWNER
L_STCU_A OWNER
L_STCU_DDR OWNER
L_STCU_N OWNER
L_STCU_NPUMIX OWNER
# Pins
PIN_FCCU_ERR0 OWNER
PIN_I2C1_SCL OWNER
PIN_I2C1_SDA OWNER
PIN_PDM_BIT_STREAM1 OWNER
PIN_UART2_RXD OWNER
PIN_UART2_TXD OWNER
PIN_WDOG_ANY OWNER
# Memory
M33_ROM EXEC, begin=0x000000000, end=0x00003FFFF
M33_TCM_CODE EXEC, begin=0x0201C0000, size=256K
M33_TCM_SYS EXEC, begin=0x020200000, size=256K
M7MIX DATA, begin=0x04A050000, end=0x04A0AFFFF
# Faults
FAULT_SW3 OWNER, reaction=grp_reset
FAULT_SW4 OWNER, reaction=sys_reset
FAULT_DRAM OWNER, reaction=sys_reset
#==========================================================================#
# M7 EENV #
#==========================================================================#
LM1 name="M7", rpc=scmi, boot=2, skip=1, did=4, safe=seenv
DFMT0: sa=secure
DFMT1: sa=secure, pa=privileged
OWNER: perm=rw, api=all
EXEC: perm=full
DATA: perm=rw
# Start/Stop (mSel=0)
PD_M7 start=1, stop=2
CPU_M7P start=2, stop=1
# Start/Stop (mSel=1)
MODE msel=1, boot=2
PD_M7 msel=1, start=1, stop=2
CPU_M7P msel=1, start=2, stop=1
# Start/Stop (mSel=2)
PD_M7 msel=2, start=1, stop=2
CPU_M7P msel=2, start=2, stop=1
# RPC Interface
SCMI_AGENT0 name="M7"
MAILBOX type=mu, mu=9, test=8, priority=high
CHANNEL db=0, xport=smt, check=crc32, rpc=scmi, type=a2p, \
test=default
CHANNEL db=1, xport=smt, check=crc32, rpc=scmi, \
type=p2a_notify, notify=24
CHANNEL db=2, xport=smt, check=crc32, rpc=scmi, \
type=p2a_priority
# API
BRD_SM_CTRL_BUTTON NOTIFY
BRD_SM_CTRL_PCA2131 ALL
BRD_SM_CTRL_TEST ALL
BRD_SM_CTRL_TEST_A ALL
BRD_SM_RTC_PCA2131 ALL
BRD_SM_SENSOR_TEMP_PF09 SET
BRD_SM_SENSOR_TEMP_PF5301 SET
BRD_SM_SENSOR_TEMP_PF5302 SET
BUTTON NOTIFY
FUSA ALL
LMM_2 ALL
RTC PRIV
SENSOR_TEMP_ANA ALL
SYS ALL
# Resources
M7P OWNER # CPUs must be first
CAN_FD1 OWNER
FSB READONLY
IRQSTEER_M7 OWNER
LPIT1 OWNER
LPTMR1 OWNER
LPTMR2 OWNER
LPTPM1 OWNER
LPUART3 OWNER, test
MSGINTR1 OWNER
MSGINTR2 OWNER
MU5_A OWNER
MU7_B OWNER
MU8_B OWNER
MU_ELE5 OWNER
PD_M7 test
SYSCTR_RD READONLY
TSTMR2 OWNER
V2X_SHE1 OWNER
WDOG5 OWNER
# Pins
PIN_GPIO_IO14 OWNER
PIN_GPIO_IO15 OWNER
# Memory
M7MIX DATA, begin=0x020380000, end=0x02047FFFF
M7MIX DATA, begin=0x04A060000, end=0x04A09FFFF
DDR EXEC, begin=0x080000000, end=0x089FFFFFF
# Faults
FAULT_M7_LOCKUP OWNER, reaction=lm_reset
FAULT_M7_RESET OWNER, reaction=lm_reset
FAULT_SW0 OWNER, reaction=fusa
FAULT_SW1 OWNER, reaction=lm_reset
FAULT_WDOG5 OWNER, reaction=lm_reset
#==========================================================================#
# A55 secure EENV #
#==========================================================================#
LM2 name="AP", rpc=scmi, boot=3, skip=1, did=3, default
DFMT0: sa=bypass
DFMT1: sa=secure, pa=privileged
OWNER: perm=sec_rw, api=all
EXEC: perm=sec_rwx
DATA: perm=sec_rw
# Start/Stop (mSel=0)
VOLT_ARM start=1|1, stop=9
PD_A55P start=2, stop=8, test
PD_A55C0 stop=7
PD_A55C1 stop=6
PD_A55C2 stop=5
PD_A55C3 stop=4
PD_A55C4 stop=3
PD_A55C5 stop=2
PERF_A55 start=3|3
CPU_A55C0 start=4
CPU_A55P stop=1
# Start/Stop (mSel=1)
VOLT_ARM msel=1, start=1|1, stop=9
PD_A55P msel=1, start=2, stop=8
PD_A55C0 msel=1, stop=7
PD_A55C1 msel=1, stop=6
PD_A55C2 msel=1, stop=5
PD_A55C3 msel=1, stop=4
PD_A55C4 msel=1, stop=3
PD_A55C5 msel=1, stop=2
PERF_A55 msel=1, start=3|3
CPU_A55C0 msel=1, start=4
CPU_A55P msel=1, stop=1
# Start/Stop (mSel=2)
VOLT_ARM msel=2, start=1|1, stop=9
PD_A55P msel=2, start=2, stop=8
PD_A55C0 msel=2, stop=7
PD_A55C1 msel=2, stop=6
PD_A55C2 msel=2, stop=5
PD_A55C3 msel=2, stop=4
PD_A55C4 msel=2, stop=3
PD_A55C5 msel=2, stop=2
PERF_A55 msel=2, start=3|3
CPU_A55C0 msel=2, start=4
CPU_A55P msel=2, stop=1
# RPC Interface
SCMI_AGENT1 name="AP-S", secure
MAILBOX type=mu, mu=1, test=0
CHANNEL db=0, xport=smt, rpc=scmi, type=a2p
CHANNEL db=1, xport=smt, rpc=scmi, type=p2a_notify
# API
PERF_A55 ALL
PERLPI_CAN2 ALL
PERLPI_CAN3 ALL
PERLPI_CAN4 ALL
PERLPI_CAN5 ALL
PERLPI_GPIO2 ALL
PERLPI_GPIO3 ALL
PERLPI_GPIO4 ALL
PERLPI_GPIO5 ALL
PERLPI_LPUART1 ALL
PERLPI_LPUART4 ALL
PERLPI_LPUART5 ALL
PERLPI_LPUART6 ALL
PERLPI_LPUART7 ALL
PERLPI_LPUART8 ALL
PERLPI_WDOG3 ALL
PERLPI_WDOG4 ALL
SYS ALL
# Resources
A55C0 OWNER # CPUs must be first
A55C1 OWNER # CPUs must be first
A55C2 OWNER # CPUs must be first
A55C3 OWNER # CPUs must be first
A55C4 OWNER # CPUs must be first
A55C5 OWNER # CPUs must be first
A55P OWNER, sema=0x442313F8
ARM_PLL OWNER
MU1_A OWNER
MU_ELE1 OWNER
MU_ELE2 OWNER
# Pins
# Memory
OCRAM EXEC, begin=0x020480000, size=256K
DDR EXEC, begin=0x08A000000, end=0x08DFFFFFF
# Faults
FAULT_SW2 OWNER, reaction=lm_reset
FAULT_WDOG3 OWNER, reaction=lm_reset
FAULT_WDOG4 OWNER, reaction=lm_reset
#==========================================================================#
# A55 non-secure EENV #
#==========================================================================#
DFMT0: sa=nonsecure
DFMT1: sa=nonsecure, pa=privileged
OWNER: perm=rw, api=all
ACCESS: perm=rw, api=all, mdid=none
EXEC: perm=full
DATA: perm=rw
# RPC Interface
SCMI_AGENT2 name="AP-NS"
MAILBOX type=mu, mu=3, test=2
CHANNEL db=0, xport=smt, rpc=scmi, type=a2p
CHANNEL db=1, xport=smt, rpc=scmi, type=p2a_notify
# API
AUDIO_PLL1 ALL
AUDIO_PLL2 ALL
BRD_SM_CTRL_BT_WAKE NOTIFY
BRD_SM_CTRL_BUTTON NOTIFY
BRD_SM_CTRL_PCIE1_WAKE NOTIFY
BRD_SM_CTRL_PCIE2_WAKE NOTIFY
BRD_SM_CTRL_SD3_WAKE NOTIFY
BRD_SM_CTRL_TEST_A ALL
BRD_SM_RTC_PCA2131 PRIV
BRD_SM_SENSOR_TEMP_PF09 ALL
BRD_SM_SENSOR_TEMP_PF5301 SET
BRD_SM_SENSOR_TEMP_PF5302 SET
BUTTON ALL, test
CLOCK_DISP1PIX ALL
CLOCK_EXT ALL
CLOCK_EXT1 ALL
CLOCK_EXT2 ALL
CLOCK_HSIOPCIEAUX ALL
CLOCK_OUT1 ALL
CLOCK_OUT2 ALL
CLOCK_OUT3 ALL
CLOCK_OUT4 ALL
CLOCK_USBPHYBURUNIN ALL
CLOCK_VPUDSP ALL
HSIO_PLL ALL
LDB_PLL ALL
LMM_1 NOTIFY
PERF_A55 ALL
RTC ALL, test
SENSOR_TEMP_A55 ALL
SENSOR_TEMP_ANA SET
SYS NOTIFY
# Resources
ADC OWNER
BLK_CTRL_CAMERAMIX OWNER
BLK_CTRL_DISPLAYMIX OWNER
BLK_CTRL_HSIOMIX OWNER
BLK_CTRL_NETCMIX OWNER
BLK_CTRL_NPUMIX OWNER
BLK_CTRL_VPUMIX OWNER
CAMERA1 OWNER
CAMERA2 OWNER
CAMERA3 OWNER
CAMERA4 OWNER
CAMERA5 OWNER
CAMERA6 OWNER
CAMERA7 OWNER
CAMERA8 OWNER
CAN_FD2 OWNER
CAN_FD3 OWNER
CAN_FD4 OWNER
CAN_FD5 OWNER
DC OWNER, test
DC0 OWNER
DC1 OWNER
DC_2DBLIT OWNER
DC_BLITINT OWNER
DC_CMDSEQ OWNER
DC_DISPENG OWNER
DC_DISPENG_INT OWNER
DC_FL0 OWNER
DC_FL1 OWNER
DC_INT_CTL OWNER
DC_PIXENGINE OWNER
DC_XPC OWNER
DC_YUV0 OWNER
DC_YUV1 OWNER
DC_YUV2 OWNER
DC_YUV3 OWNER
DDR_PM ACCESS
EDMA1_MP OWNER
EDMA1_CH0 OWNER
EDMA1_CH1 OWNER
EDMA1_CH2 OWNER
EDMA1_CH3 OWNER
EDMA1_CH4 OWNER
EDMA1_CH5 OWNER
EDMA1_CH6 OWNER
EDMA1_CH7 OWNER
EDMA1_CH8 OWNER
EDMA1_CH9 OWNER
EDMA1_CH10 OWNER
EDMA1_CH11 OWNER
EDMA1_CH12 OWNER
EDMA1_CH13 OWNER
EDMA1_CH14 OWNER
EDMA1_CH15 OWNER
EDMA1_CH16 OWNER
EDMA1_CH17 OWNER
EDMA1_CH18 OWNER
EDMA1_CH19 OWNER
EDMA1_CH20 OWNER
EDMA1_CH21 OWNER
EDMA1_CH22 OWNER
EDMA1_CH23 OWNER
EDMA1_CH24 OWNER
EDMA1_CH25 OWNER
EDMA1_CH26 OWNER
EDMA1_CH27 OWNER
EDMA1_CH28 OWNER
EDMA1_CH29 OWNER
EDMA1_CH30 OWNER
EDMA1_CH31 OWNER
EDMA2_MP ACCESS
EDMA2_CH2_3 OWNER
EDMA2_CH4_5 OWNER
EDMA2_CH6_7 OWNER
EDMA2_CH8_9 OWNER
EDMA2_CH10_11 OWNER
EDMA2_CH12_13 OWNER
EDMA2_CH14_15 OWNER
EDMA2_CH16_17 OWNER
EDMA2_CH18_19 OWNER
EDMA2_CH20_21 OWNER
EDMA2_CH22_23 OWNER
EDMA2_CH24_25 OWNER
EDMA2_CH26_27 OWNER
EDMA2_CH28_29 OWNER
EDMA2_CH30_31 OWNER
EDMA2_CH32_33 OWNER
EDMA2_CH34_35 OWNER
EDMA2_CH36_37 OWNER
EDMA2_CH38_39 OWNER
EDMA2_CH40_41 OWNER
EDMA2_CH42_43 OWNER
EDMA2_CH44_45 OWNER
EDMA2_CH46_47 OWNER
EDMA2_CH48_49 OWNER
EDMA2_CH50_51 OWNER
EDMA2_CH52_53 OWNER
EDMA2_CH54_55 OWNER
EDMA2_CH56_57 OWNER
EDMA2_CH58_59 OWNER
EDMA2_CH60_61_A OWNER
EDMA2_CH60_61_B OWNER
EDMA2_CH62_63_A OWNER
EDMA2_CH62_63_B OWNER
EDMA3_MP OWNER
EDMA3_CH0_1 OWNER
EDMA3_CH2_3 OWNER
EDMA3_CH4_5 OWNER
EDMA3_CH6_7 OWNER
EDMA3_CH8_9 OWNER
EDMA3_CH10_11 OWNER
EDMA3_CH12_13 OWNER
EDMA3_CH14_15 OWNER
EDMA3_CH16_17 OWNER
EDMA3_CH18_19 OWNER
EDMA3_CH20_21 OWNER
EDMA3_CH22_23 OWNER
EDMA3_CH24_25 OWNER
EDMA3_CH26_27 OWNER
EDMA3_CH28_29 OWNER
EDMA3_CH30_31 OWNER
EDMA3_CH32_33 OWNER
EDMA3_CH34_35 OWNER
EDMA3_CH36_37 OWNER
EDMA3_CH38_39 OWNER
EDMA3_CH40_41 OWNER
EDMA3_CH42_43 OWNER
EDMA3_CH44_45 OWNER
EDMA3_CH46_47 OWNER
EDMA3_CH48_49 OWNER
EDMA3_CH50_51 OWNER
EDMA3_CH52_53 OWNER
EDMA3_CH54_55 OWNER
EDMA3_CH56_57 OWNER
EDMA3_CH58_59 OWNER
EDMA3_CH60_61 OWNER
EDMA3_CH62_63 OWNER
FLEXIO1 OWNER
FLEXIO2 OWNER
FLEXSPI1 OWNER
FSB READONLY
GIC OWNER
GPIO2 OWNER
GPIO3 OWNER
GPIO4 OWNER
GPIO5 OWNER
GPR4 OWNER, test
GPR5 OWNER
GPR6 OWNER
GPR7 OWNER
GPU_NPROT OWNER, test
GPU_PROT OWNER, test
I3C1 OWNER
I3C2 OWNER
ISI1 OWNER
ISI2 OWNER
ISI3 OWNER
ISI4 OWNER
ISI5 OWNER
ISI6 OWNER
ISI7 OWNER
ISI8 OWNER
ISP_CPU OWNER
ISP_MGR OWNER, test
JPEG_DEC OWNER
LPI2C2 OWNER
LPI2C3 OWNER
LPI2C4 OWNER
LPI2C5 OWNER
LPI2C6 OWNER
LPI2C7 OWNER
LPI2C8 OWNER
LPIT2 OWNER
LPSPI1 OWNER
LPSPI2 OWNER
LPSPI3 OWNER
LPSPI4 OWNER
LPSPI5 OWNER
LPSPI6 OWNER
LPSPI7 OWNER
LPSPI8 OWNER
LPTPM2 OWNER
LPTPM3 OWNER
LPTPM4 OWNER
LPTPM5 OWNER
LPTPM6 OWNER
LPUART1 OWNER
LPUART4 OWNER
LPUART5 OWNER
LPUART6 OWNER
LPUART7 OWNER
LPUART8 OWNER, test
LVDS OWNER
MIPI_CSI0 OWNER
MIPI_CSI1 OWNER
MIPI_DSI OWNER
MIPI_PHY OWNER
MJPEG_DEC1 OWNER
MJPEG_DEC2 OWNER
MJPEG_DEC3 OWNER
MJPEG_DEC4 OWNER
MJPEG_ENC OWNER
MJPEG_ENC1 OWNER
MJPEG_ENC2 OWNER
MJPEG_ENC3 OWNER
MJPEG_ENC4 OWNER
MU2_A OWNER
MU3_A OWNER
MU4_A OWNER
MU6_A OWNER
MU7_A OWNER
MU8_A OWNER
MU_ELE3 OWNER
MU_ELE4 OWNER
NETC OWNER, test
NETC0 OWNER
NETC1 OWNER
NETC2 OWNER
NETC_ECAM OWNER
NETC_EMDIO0 OWNER
NETC_IERB OWNER
NETC_LDID1 OWNER, kpa=0, sid=0x20
NETC_LDID2 OWNER, kpa=0, sid=0x21
NETC_LDID3 OWNER, kpa=0, sid=0x22
NETC_LDID4 OWNER, kpa=0, sid=0x23
NETC_LDID5 OWNER, kpa=0, sid=0x24
NETC_LDID6 OWNER, kpa=0, sid=0x25
NETC_LDID7 OWNER, kpa=0, sid=0x26
NETC_LDID8 OWNER, kpa=0, sid=0x27
NETC_PRB OWNER
NETC_TIMER0 OWNER
NETC_VSI0 OWNER
NETC_VSI1 OWNER
NETC_VSI2 OWNER
NETC_VSI3 OWNER
NETC_VSI4 OWNER
NETC_VSI5 OWNER
NPU OWNER, kpa=0, sid=0x0d, test
PCI1_LUT0 OWNER, kpa=0, sid=0x10
PCI1_LUT1 OWNER, kpa=0, sid=0x11
PCI1_LUT2 OWNER, kpa=0, sid=0x12
PCI1_LUT3 OWNER, kpa=0, sid=0x13
PCI1_LUT4 OWNER, kpa=0, sid=0x14
PCI1_LUT5 OWNER, kpa=0, sid=0x15
PCI1_LUT6 OWNER, kpa=0, sid=0x16
PCI1_LUT7 OWNER, kpa=0, sid=0x17
PCI2_LUT0 OWNER, kpa=0, sid=0x18
PCI2_LUT1 OWNER, kpa=0, sid=0x19
PCI2_LUT2 OWNER, kpa=0, sid=0x1a
PCI2_LUT3 OWNER, kpa=0, sid=0x1b
PCI2_LUT4 OWNER, kpa=0, sid=0x1c
PCI2_LUT5 OWNER, kpa=0, sid=0x1d
PCI2_LUT6 OWNER, kpa=0, sid=0x1e
PCI2_LUT7 OWNER, kpa=0, sid=0x1f
PCIE1_OUT OWNER
PCIE1_ROOT OWNER
PCIE2_OUT OWNER
PCIE2_ROOT OWNER
PDM OWNER
SAI1 OWNER, test
SAI2 OWNER
SAI3 OWNER
SAI4 OWNER
SAI5 OWNER
SEMA41 OWNER
SEMA42 OWNER
SMMU OWNER
SPDIF1 OWNER
SYSCTR_CMP OWNER
SYSCTR_RD_STOP READONLY
USB1 OWNER, kpa=0, sid=0xe, test
USB2 OWNER, kpa=0, sid=0xf
USDHC1 OWNER, kpa=0, sid=0x1
USDHC2 OWNER, kpa=0, sid=0x2
USDHC3 OWNER, kpa=0, sid=0x3
V2X_APP0 OWNER
V2X_DEBUG OWNER
V2X_HSM1 OWNER
V2X_HSM2 OWNER
V2X_SHE0 OWNER
VIDEO_PLL1 OWNER
VPU OWNER, test
VPU1 OWNER
VPU2 OWNER
VPU3 OWNER
VPU4 OWNER
WDOG3 OWNER
WDOG4 OWNER
XSPI OWNER
# Pins
PIN_CCM_CLKO1 OWNER
PIN_CCM_CLKO2 OWNER
PIN_CCM_CLKO3 OWNER
PIN_CCM_CLKO4 OWNER
PIN_DAP_TCLK_SWCLK OWNER
PIN_DAP_TDI OWNER
PIN_DAP_TDO_TRACESWO OWNER
PIN_DAP_TMS_SWDIO OWNER
PIN_ENET1_MDC OWNER
PIN_ENET1_MDIO OWNER
PIN_ENET1_RD0 OWNER
PIN_ENET1_RD1 OWNER
PIN_ENET1_RD2 OWNER
PIN_ENET1_RD3 OWNER
PIN_ENET1_RX_CTL OWNER
PIN_ENET1_RXC OWNER
PIN_ENET1_TD0 OWNER
PIN_ENET1_TD1 OWNER
PIN_ENET1_TD2 OWNER
PIN_ENET1_TD3 OWNER
PIN_ENET1_TX_CTL OWNER
PIN_ENET1_TXC OWNER
PIN_ENET2_MDC OWNER
PIN_ENET2_MDIO OWNER
PIN_ENET2_RD0 OWNER
PIN_ENET2_RD1 OWNER
PIN_ENET2_RD2 OWNER
PIN_ENET2_RD3 OWNER
PIN_ENET2_RX_CTL OWNER
PIN_ENET2_RXC OWNER
PIN_ENET2_TD0 OWNER
PIN_ENET2_TD1 OWNER
PIN_ENET2_TD2 OWNER
PIN_ENET2_TD3 OWNER
PIN_ENET2_TX_CTL OWNER
PIN_ENET2_TXC OWNER
PIN_GPIO_IO00 OWNER
PIN_GPIO_IO01 OWNER
PIN_GPIO_IO02 OWNER
PIN_GPIO_IO03 OWNER
PIN_GPIO_IO04 OWNER
PIN_GPIO_IO05 OWNER
PIN_GPIO_IO06 OWNER
PIN_GPIO_IO07 OWNER
PIN_GPIO_IO08 OWNER
PIN_GPIO_IO09 OWNER
PIN_GPIO_IO10 OWNER
PIN_GPIO_IO11 OWNER
PIN_GPIO_IO12 OWNER
PIN_GPIO_IO13 OWNER
PIN_GPIO_IO16 OWNER
PIN_GPIO_IO17 OWNER
PIN_GPIO_IO18 OWNER
PIN_GPIO_IO19 OWNER
PIN_GPIO_IO20 OWNER
PIN_GPIO_IO21 OWNER
PIN_GPIO_IO22 OWNER
PIN_GPIO_IO23 OWNER
PIN_GPIO_IO24 OWNER
PIN_GPIO_IO25 OWNER
PIN_GPIO_IO26 OWNER
PIN_GPIO_IO27 OWNER
PIN_GPIO_IO28 OWNER
PIN_GPIO_IO29 OWNER
PIN_GPIO_IO30 OWNER
PIN_GPIO_IO31 OWNER
PIN_GPIO_IO32 OWNER
PIN_GPIO_IO33 OWNER
PIN_GPIO_IO34 OWNER
PIN_GPIO_IO35 OWNER
PIN_GPIO_IO36 OWNER
PIN_GPIO_IO37 OWNER
PIN_I2C2_SCL OWNER
PIN_I2C2_SDA OWNER
PIN_PDM_BIT_STREAM0 OWNER
PIN_PDM_CLK OWNER
PIN_SAI1_RXD0 OWNER
PIN_SAI1_TXC OWNER
PIN_SAI1_TXD0 OWNER
PIN_SAI1_TXFS OWNER
PIN_SD1_CLK OWNER
PIN_SD1_CMD OWNER
PIN_SD1_DATA0 OWNER
PIN_SD1_DATA1 OWNER
PIN_SD1_DATA2 OWNER
PIN_SD1_DATA3 OWNER
PIN_SD1_DATA4 OWNER
PIN_SD1_DATA5 OWNER
PIN_SD1_DATA6 OWNER
PIN_SD1_DATA7 OWNER
PIN_SD1_STROBE OWNER
PIN_SD2_CD_B OWNER
PIN_SD2_CLK OWNER
PIN_SD2_CMD OWNER
PIN_SD2_DATA0 OWNER
PIN_SD2_DATA1 OWNER
PIN_SD2_DATA2 OWNER
PIN_SD2_DATA3 OWNER
PIN_SD2_RESET_B OWNER
PIN_SD2_VSELECT OWNER
PIN_SD3_CLK OWNER
PIN_SD3_CMD OWNER
PIN_SD3_DATA0 OWNER
PIN_SD3_DATA1 OWNER
PIN_SD3_DATA2 OWNER
PIN_SD3_DATA3 OWNER
PIN_UART1_RXD OWNER, test
PIN_UART1_TXD OWNER
PIN_XSPI1_DATA0 OWNER
PIN_XSPI1_DATA1 OWNER
PIN_XSPI1_DATA2 OWNER
PIN_XSPI1_DATA3 OWNER
PIN_XSPI1_DATA4 OWNER
PIN_XSPI1_DATA5 OWNER
PIN_XSPI1_DATA6 OWNER
PIN_XSPI1_DATA7 OWNER
PIN_XSPI1_DQS OWNER
PIN_XSPI1_SCLK OWNER
PIN_XSPI1_SS0_B OWNER
PIN_XSPI1_SS1_B OWNER
# Memory
FLEXSPI1_MEM EXEC, begin=0x000000000, end=0x0FFFFFFFF
OCRAM_C EXEC, begin=0x001000000, end=0x001017FFF
OCRAM EXEC, begin=0x0204C0000, size=96K
GPU DATA, begin=0x04D900000, end=0x04DD7FFFF
DDR EXEC, begin=0x088000000, end=0x089FFFFFF, clr=8
DDR EXEC, begin=0x08E000000, end=0x87FFFFFFF
System manager main:
int main(int argc, const char * const argv[])
{
int32_t status = SM_ERR_SUCCESS;
uint64_t delta;
uint32_t mSel = 0U;
/* Store boot start time */
g_bootTime[SM_BT_START] = DEV_SM_Usec64Get();
#ifdef INC_LIBC
/* Configure stdio for no buffering */
(void) setvbuf(stdin, NULL, _IONBF, 0);
(void) setvbuf(stdout, NULL, _IONBF, 0);
#endif
/* Init the system hardware */
status = BRD_SM_Init(argc, argv, &mSel);
/* Save start banner time */
delta = DEV_SM_Usec64Get();
/* Print banner */
printf("\nHello from SM (Build %lu, Commit %08lx, %s %s)\n\n",
SM_BUILD, SM_COMMIT, SM_DATE, SM_TIME);
#if MONITOR_MODE == 2
printf("Press key to enter monitor mode.\n\n",
SM_BUILD, SM_COMMIT, SM_DATE, SM_TIME);
#endif
/* Add to subtract time */
/* Intentional: used only for debug */
/* coverity[cert_int30_c_violation] */
g_bootTime[SM_BT_SUB] += (DEV_SM_Usec64Get() - delta);
/* Init LMM */
if (status == SM_ERR_SUCCESS)
{
/* mSel from BRD_SM_Init(), LMM_INIT_FLAGS from Makefile */
status = LMM_Init(&mSel, LMM_INIT_FLAGS);
}
#ifndef SIMU
/* Start systick, disable boot WDOG */
SM_SYSTICKENABLE();
#endif
if (status == SM_ERR_SUCCESS)
{
/* Mark LMM inited */
s_lmmInited = true;
/* Boot LMs */
status = LMM_Boot();
}
#ifdef RUN_TEST
/* Init client API for test */
if (status == SM_ERR_SUCCESS)
{
status = TEST_Config();
}
#endif
/* Post-boot cleanup */
if (status == SM_ERR_SUCCESS)
{
status = LMM_PostBoot();
}
/* Report any error during init */
if (status != SM_ERR_SUCCESS)
{
printf("Init error: %d\n", status);
}
#ifdef RUN_TEST
/* Run test */
if (status == SM_ERR_SUCCESS)
{
TEST();
}
#endif
#if MONITOR_MODE == 1
/* Call monitor */
MONITOR_Cmd("\n*** SM Debug Monitor ***\n");
#endif
#ifndef SIMU
#if MONITOR_MODE == 2
/* Idle loop */
while (status == SM_ERR_SUCCESS)
{
bool runMonitor = false;
const board_uart_config_t *uartConfig = BOARD_GetDebugUart();
/* Grab sleep count to detect idle/sleep */
uint32_t prevSleepCnt = g_syslog.sysSleepRecord.sleepCnt;
/* Enter system idle */
status = DEV_SM_SystemIdle();
/* Check if system idle succeeded */
if ((status == SM_ERR_SUCCESS) && (uartConfig != NULL))
{
/* Check if if system entered sleep */
if (prevSleepCnt != g_syslog.sysSleepRecord.sleepCnt)
{
/* Check if system sleep wake source was console UART */
if (g_syslog.sysSleepRecord.wakeSource ==
(uartConfig->irq + 16U))
{
runMonitor = true;
}
}
else
{
/* Check for console character */
runMonitor = MONITOR_CharPending();
}
}
if ((status == SM_ERR_SUCCESS) && runMonitor)
{
/* Call monitor */
MONITOR_Cmd("\n*** SM Debug Monitor ***\n");
}
}
#elif !defined(RUN_TEST)
/* Loop - services handled via interrupts */
while (status == SM_ERR_SUCCESS)
{
status = DEV_SM_SystemIdle();
}
#endif
#endif
printf("\nGood-bye from SM\n\n");
return status;
}
Надо запретить загрузку M7 и A55 - и дописать код в system manager - чтобы загрузка M7 и A55 происходила по команде
