---

library ieee;
use ieee.std_logic_1164.all;

entity res_reg is
generic (
    HOLD_VALUE : boolean := false
);
port (
    clk       : in std_logic;
    slow      : in std_logic;
    clear     : in std_logic;
    value_in  : in std_logic_vector(15 downto 0);
    value_out : out std_logic_vector(15 downto 0) := (others => '0')
);
end res_reg;

architecture rtl of res_reg is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if clear = '0' then
                value_out <= (others => '0');
            else
                if HOLD_VALUE = false then
                    value_out <= value_in;
                else
                    if slow = '1' then
                        value_out <= value_in;
                    end if;
                end if;
            end if;
        end if;
    end process;
end rtl;