7.2.4 Audio Data Processing Flow
The LT9611 supports two to eight audio channels through four I2S inputs as well as one S/PDIF input of audio data. The
SPDIF stream is processed by a separate SPDIF processing block. The SPDIF processing block consists of SPDIF Frame
sync detection and data decode block, FIFOs to store the received data, validity, parity, user’s data and channel status bits for
both the left and right channels. It also has a single bit FIFO which is used to store the information regarding the first frame
detection. A depth of 16 for each of FIFOs is sufficient. The SPDIF sync detection, data decoding and loading of the decoded
data are done synchronous to the SPDIF clock. The SDPIF clock is twice the SPDIF bit-rate. This selection is done to ease the
implementation of the sync detection and data decoding. The reading of the data is done by the TMDS clock. The TMDS clock
and SPDIF clock are assumed to be asynchronous with each other. To ensure that the write pointer of the FIFO is not
corrupted when mapped from SPDIF to TMDS clock domain, the write pointer is grey coded. It is also mandatory to double re-
time the write pointer in the TMDS clock domain.
In addition to the SPDIF processing block, the audio data packetization also has a header byte generation block. This block is
responsible for generation of the header bytes for the audio packet.
The four I2S inputs allow transmission of 8-channel uncompressed audio data at up to 192 kHz sample rate. Four FIFOs are
to store the received data.
The appropriate registers must be configured to describe the format of audio being input into the LT9611. This information is
passed over the HDMI link in the CEA-861B Audio Info (AI) packets.
Four I2S inputs also allow transmission of DVD-Audio and decoded Dolby Digital to A/V Receivers and high-end displays. The
interface supports up to 2-channel 192 kHz or 8-channel 96 kHz.
Audio data carried across the HDMI link, which is driven by a TMDS (video) clock only, does not retain the original audio
sample clock. The task of recreating this clock at the Sink is called Audio Clock Regeneration.
In many video source devices, the audio and video clocks are generated from a common clock
In this situation, there exists a rational (integer divided by integer) relationship between these two clocks. The HDMI clock
regeneration architecture can take advantage of this rational relationship and can also work in an environment where there is
no such relationship between these two clocks, that is, where the two clocks are truly asynchronous or where their relationship
is unknown.
The Source shall determine the fractional relationship between the video clock and an audio reference clock.
The exact relationship between the two clocks will be:
128*fs = fTMDS_CLK * N / CTS.
The CTS value generated by the HDMI source is used by the HDMI sync to re-generate the audio sample clock. The CTS is
generated according to the equation 128*FS = pixel clock*N/CTS, where FS is the audio sample clock. In other words the CTS
is generated by counting the number of pix clocks in 128*fs/N duration. This can be implemented using simple counters. The
CTS counter has to be a 20bit counter and is initialized (to zero) after every 128*FS/N clocks.
The 128*fs and pixel clock have to be treated as asynchronous with respect to each other and appropriate care is to be taken
during synchronization.
