---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mult_controller is
    port (
        clk            : in  std_logic;
        reset_btn      : in  std_logic;
        show_ip_btn    : in  std_logic;
        show_logic_btn : in  std_logic;
        result_valid   : out std_logic;
        bcd_0          : out integer range 0 to 9;
        bcd_1          : out integer range 0 to 9;
        bcd_2          : out integer range 0 to 9;
        bcd_3          : out integer range 0 to 9;
        bcd_4          : out integer range 0 to 9
    );
end mult_controller;

architecture rtl of mult_controller is

    constant NUM_A : unsigned(7 downto 0) := to_unsigned(12, 8);
    constant NUM_B : unsigned(7 downto 0) := to_unsigned(15, 8);

    -- Сигнал Slow (импульс 1 такт после нажатия кнопки)
    signal slow_ip    : std_logic := '0';
    signal slow_logic : std_logic := '0';

    -- Выходы мультиплексоров для IP-ядра
    signal mux_a_ip : std_logic_vector(7 downto 0);
    signal mux_b_ip : std_logic_vector(7 downto 0);

    -- Выходы мультиплексоров для логического умножителя
    signal mux_a_logic : unsigned(7 downto 0);
    signal mux_b_logic : unsigned(7 downto 0);

    -- Результат IP-ядра
    signal mult_ip_result : std_logic_vector(15 downto 0) := (others => '0');

    -- Результат логического умножителя
    signal mult_logic_result : unsigned(15 downto 0) := (others => '0');

    -- Выбранный результат
    signal selected_result : unsigned(15 downto 0) := (others => '0');

    -- Регистр результата C
    signal result_reg : unsigned(15 downto 0) := (others => '0');
    signal enable_reg : std_logic := '0';

    -- BCD цифры
    signal bcd_reg_0 : integer range 0 to 9 := 0;
    signal bcd_reg_1 : integer range 0 to 9 := 0;
    signal bcd_reg_2 : integer range 0 to 9 := 0;
    signal bcd_reg_3 : integer range 0 to 9 := 0;
    signal bcd_reg_4 : integer range 0 to 9 := 0;

begin

    -- ==========================================
    -- 1. Генерация сигнала Slow для IP-кнопки
    -- ==========================================
    process(clk)
        variable slow_counter : integer range 0 to 2 := 0;
    begin
        if rising_edge(clk) then
            if reset_btn = '1' then
                slow_ip <= '0';
                slow_counter := 0;
            elsif show_ip_btn = '1' and slow_counter = 0 then
                slow_ip <= '1';
                slow_counter := 1;
            elsif slow_counter = 1 then
                slow_ip <= '0';
                slow_counter := 2;
            else
                slow_counter := 0;
            end if;
        end if;
    end process;

    -- ==========================================
    -- 2. Генерация сигнала Slow для Logic-кнопки
    -- ==========================================
    process(clk)
        variable slow_counter : integer range 0 to 2 := 0;
    begin
        if rising_edge(clk) then
            if reset_btn = '1' then
                slow_logic <= '0';
                slow_counter := 0;
            elsif show_logic_btn = '1' and slow_counter = 0 then
                slow_logic <= '1';
                slow_counter := 1;
            elsif slow_counter = 1 then
                slow_logic <= '0';
                slow_counter := 2;
            else
                slow_counter := 0;
            end if;
        end if;
    end process;

    -- ==========================================
    -- 3. Мультиплексоры для IP-ядра
    -- ==========================================
    -- MUX A: если slow_ip='1' то A, иначе 0
    mux_a_ip <= std_logic_vector(NUM_A) when slow_ip = '1' else (others => '0');
    
    -- MUX B: если slow_ip='1' то B, иначе 0
    mux_b_ip <= std_logic_vector(NUM_B) when slow_ip = '1' else (others => '0');

    -- ==========================================
    -- 4. IP-ядро умножителя
    -- ==========================================
    u_mult_ip : entity work.mult_ip
        port map (
            dataa  => mux_a_ip,
            datab  => mux_b_ip,
            result => mult_ip_result
        );

    -- ==========================================
    -- 5. Мультиплексоры для логического умножителя
    -- ==========================================
    -- MUX A: если slow_logic='1' то A, иначе 0
    mux_a_logic <= NUM_A when slow_logic = '1' else (others => '0');
    
    -- MUX B: если slow_logic='1' то B, иначе 0
    mux_b_logic <= NUM_B when slow_logic = '1' else (others => '0');

    -- ==========================================
    -- 6. Логический умножитель (Shift-and-Add с MUX)
    -- ==========================================
    process(mux_a_logic, mux_b_logic)
        variable temp_result : unsigned(15 downto 0);
    begin
        temp_result := (others => '0');
        
        -- Умножение через сдвиг и сложение
        for i in 0 to 7 loop
            if mux_b_logic(i) = '1' then
                temp_result := temp_result + (mux_a_logic sll i);
            end if;
        end loop;
        
        mult_logic_result <= temp_result;
    end process;

    -- ==========================================
    -- 7. Сохранение результата в регистр C
    -- ==========================================
    process(clk)
    begin
        if rising_edge(clk) then
            if reset_btn = '1' then
                result_reg <= (others => '0');
                enable_reg <= '0';
            elsif slow_ip = '1' then
                result_reg <= unsigned(mult_ip_result);
                enable_reg <= '1';
            elsif slow_logic = '1' then
                result_reg <= mult_logic_result;
                enable_reg <= '1';
            end if;
        end if;
    end process;

    -- ==========================================
    -- 8. Преобразование в BCD
    -- ==========================================
    process(clk)
    begin
        if rising_edge(clk) then
            if reset_btn = '1' then
                bcd_reg_0 <= 0; bcd_reg_1 <= 0; bcd_reg_2 <= 0;
                bcd_reg_3 <= 0; bcd_reg_4 <= 0;
            elsif enable_reg = '1' then
                bcd_reg_0 <= to_integer((result_reg / 10000) mod 10);
                bcd_reg_1 <= to_integer((result_reg / 1000) mod 10);
                bcd_reg_2 <= to_integer((result_reg / 100) mod 10);
                bcd_reg_3 <= to_integer((result_reg / 10) mod 10);
                bcd_reg_4 <= to_integer(result_reg mod 10);
            end if;
        end if;
    end process;

    result_valid <= enable_reg;
    bcd_0 <= bcd_reg_0;
    bcd_1 <= bcd_reg_1;
    bcd_2 <= bcd_reg_2;
    bcd_3 <= bcd_reg_3;
    bcd_4 <= bcd_reg_4;

end rtl;