---

module ram_16x8 (A, D, Q, WE, CLK, RES_N);

input wire [3:0] A;
input wire [7:0] D;
input wire CLK, WE, RES_N;
output reg [7:0] Q;

reg [7:0] RAM [15:0];

integer i;

always @(*) begin
Q = RAM[A];
end

always @(posedge CLK or negedge RES_N) begin
if(!RES_N) begin
for (i = 0; i < 16; i = i+1) begin
RAM [A] <= 8'h0;
end
end else if (WE) begin
RAM [A] <= D;
end
end

endmodule