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1. AUDIO_XCVR PHY: Used to receive SPDIF data from the SPDIF input.
2. AUDIO_XCVR Controller : Used to process the received audio data or the audio data that needs to be transmitted (SPDIF).
78.2.2 Features
The AUDIO_XCVR Controller can operate in one of the following modes:
• SPDIF Receiver:
— Support for 32kHz - 192kHz sample rate
• SPDIF Transmitter:
— Support for 32kHz - 192kHz sample rate
78.3 Functional description
The following sections describe functional details of the AUDIO_XCVR.
78.3.1 Audio data format support
All SPDIF message formats use IEC60958 framing. Data is stored in the FIFO in Big endian in 2 possible formats:
1. IEC60958 data that does not need ECC protection.
• 31:28 - Preamble. For TX, the preamble can be added by Hardware or stored in the FIFO with the correct value. For
RX, the 3rd bit will be replaced by MUTE and 4th bit will be replaced by Parity error if either one is detected.
• 27:4 - TX data
• 3:0 - V, U, C and P. For TX, these bits can be added by HW or stored in the FIFO with the correct value.
Each sub-frame can be stored in memory in the reverse order, bit 31 is stored in position 0 and so on using register bit:
FRM_FMT[TX_DATAPATH_CTRL] and STORE_FMT[RX_DATAPATH_CTRL].
2. IEC61937 data that requires ECC protection
• 31:28 - Preamble. For TX, the preamble can be added by HW or stored in the FIFO with the correct value. For RX, the
3rd bit will be replaced by MUTE and 4th bit will be replaced by Parity error.
• 27:12 - 16 bits of data. (MSB is stored in bit 27)
• 11:4 - Not used. 8bit's 0.
• 3:0 - V, U, C and P. For TX, these bits can be added by HW or stored in the FIFO with the correct value.
Each sub-frame can be stored in memory in the reverse order, bit 31 is stored in position 0 and so on using register bit:
FRM_FMT in TX_DATAPATH_CTRL and STORE_FMT in RX_dATAPATH_CTRL.