---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity calculator_top is
port (
	clk : in std_logic;
	key : in std_logic_vector(2 downto 0); 
	dig : out std_logic_vector(3 downto 0);
	seg : out std_logic_vector(7 downto 0)
	);
end calculator_top;

architecture structural of calculator_top is

	signal clk_fast : std_logic;
	signal pll_locked : std_logic;
	
	signal a_val : std_logic_vector(7 downto 0);
	signal b_val : std_logic_vector(7 downto 0);

	signal state : std_logic_vector(1 downto 0);
	signal mult_en : std_logic;
	signal save_en : std_logic;
	signal disp_en : std_logic;
	signal mode : std_logic;  -- '0' = logic, '1' = dsp

	signal mux_a_out : std_logic_vector(7 downto 0);
	signal mux_b_out : std_logic_vector(7 downto 0);
	signal reg_a_out : std_logic_vector(7 downto 0);
	signal reg_b_out : std_logic_vector(7 downto 0);


	signal dsp_result : std_logic_vector(15 downto 0);
	signal logic_result : std_logic_vector(15 downto 0);
	signal selected_result : std_logic_vector(15 downto 0);
	--signal result_reg_out : std_logic_vector(15 downto 0);
	--signal disp_reg_out : std_logic_vector(15 downto 0);
	signal reg_reg1: std_logic_vector(15 downto 0);
	signal reg_reg2: std_logic_vector(15 downto 0);
	signal save_en_delayed: std_logic;

	signal display_data : std_logic_vector(31 downto 0);
	signal display_mode : std_logic_vector(7 downto 0);
	
	signal disp_en_sync1: std_logic;
	signal disp_en_sync2: std_logic;
	signal result_sync1 : std_logic_vector(15 downto 0);
	signal result_sync2 : std_logic_vector(15 downto 0);
	signal result_latched : std_logic_vector(15 downto 0);

begin
	
	U_PLL: entity work.pll_5
		port map (
			areset=>'0',
			inclk0=>clk,
			c0=>clk_fast,
			locked=>pll_locked
		);
	U_OPERAND_INT: entity work.operand_init
		port map (
			clk=>clk_fast,
			a_val=>a_val,
			b_val=>b_val
		);
	
	U_MODE_SELECT: entity work.mode_select
		port map (
			clk=>clk,
			key=> key,
			mode=>mode
		);
	
	U_MODE_DSIP: entity work.mode_display
		port map (
			clk=>clk,
			mode=>mode,
			mode_seg=>display_mode
		);

	U_CONTROL: entity work.mult_control
		port map (
			clk => clk_fast,
			reset => key(0),
			mult_en => mult_en,
			save_en => save_en,
			disp_en => disp_en,
			state_out => state
		);
	
	U_MULT_DSP: entity work.mult_5
		port map (
			dataa => reg_a_out,
			datab => reg_b_out,
			result => dsp_result
		);

	U_MULT_LOGIC: entity work.logic
		port map (
			a => reg_a_out,
			b => reg_b_out,
			result => logic_result
		);

	-- Мультиплексор + регистр для A
	U_MUX_REG_A: entity work.mux_register
		port map (
			clk => clk_fast,
			sel => mult_en,
			data_a => a_val,
			data_b => (others => '0'),
			mux_out => mux_a_out,
			q => reg_a_out
		);

	-- Мультиплексор + регистр для B
	U_MUX_REG_B: entity work.mux_register
		port map (
			clk => clk_fast,
			sel => mult_en,
			data_a => b_val,
			data_b => (others => '0'),
			mux_out => mux_b_out,
			q => reg_b_out
		);

	-- Мультиплексор выбора результата
	U_RESULT_MUX: entity work.result_mux
		port map (
			mode => mode,
			logic_res => logic_result,
			dsp_res => dsp_result,
			result_out => selected_result
		);
	U_RES_REG1: entity work.result_mux
		generic map (HOLD_VALUE=>false)
		port map (
			clk=>clk_fast,
			slow=>save_en,
			clear=>key(0),
			value_in=>selected_result,
			value_out=>res_reg1
		);
	
	process(clk_fast)
	begin
		if rising_edge(clk) then
			save_en_delayed<=save_en;
		end if;
	end process;
	
	U_RES_REG2: entity work.res_reg
		generic map (HOLD_VALUE=>true)
		port map (
			clk=>clk_fast,
			slow=>save_en_delayed,
			clear=>key(0),
			value_in=>res_reg1,
			value_out=>res_reg2
		);
	-- Регистр результата
	--U_RESULT_REG: entity work.result_register
		--port map (
			--clk => clk_fast,
			--load => save_en,
			--clear => mult_en,
			--data_in => selected_result,
			--data_out => result_reg_out
		--);
	--U_DISP_REG: entity work.display_register
		--port map (
			--clk=>clk,   
			--load=>disp_en,
			--data_in=>result_reg_out,
		--	data_out=>disp_reg_out
		--);
	U_BIN_TO_DISP: entity work.bin_to_display
		port map (
			bin_in => reg_reg2,
			seg_out => display_data
		);

	U_DISPLAY: entity work.display_scan
		port map (
			clk => clk,
			seg_in => display_data,
			mode_seg => display_mode,
			dig => dig,
			seg => seg
		);

end structural;