---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity operand_init is
port (
    clk   : in std_logic;
    a_val : out std_logic_vector(7 downto 0);
    b_val : out std_logic_vector(7 downto 0)
);
end operand_init;

architecture rtl of operand_init is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            a_val <= std_logic_vector(to_unsigned(5, 8));  -- A = 5
            b_val <= std_logic_vector(to_unsigned(7, 8));  -- B = 7
        end if;
    end process;
end rtl;

library ieee;
use ieee.std_logic_1164.all;

entity mode_select is
port (
    clk  : in std_logic;
    key  : in std_logic_vector(2 downto 0);
    mode : out std_logic
);
end mode_select;

architecture rtl of mode_select is
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if key(0) = '0' then
                mode <= '0';  -- По сбросу режим logic
            elsif key(1) = '0' then
                mode <= '0';  -- Режим logic
            elsif key(2) = '0' then
                mode <= '1';  -- Режим DSP
            end if;
        end if;
    end process;
end rtl;