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/* Inhibit all GPC LP handshakes during SUSPEND */
uint32_t lpHsSm = BLK_CTRL_S_AONMIX->LP_HANDSHAKE_SM;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE_SM = 0U;
uint32_t lpHs2Sm = BLK_CTRL_S_AONMIX->LP_HANDSHAKE2_SM;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE2_SM = 0U;
uint32_t lpHsEle = BLK_CTRL_S_AONMIX->LP_HANDSHAKE_ELE;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE_ELE = 0U;
uint32_t lpHs2Ele = BLK_CTRL_S_AONMIX->LP_HANDSHAKE2_ELE;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE2_ELE = 0U;
/* Configure SM GPC_CTRL and NVIC for system-level wake events */
for (uint32_t wakeIdx = 0;
wakeIdx < GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT;
wakeIdx++)
{
/* Save context of SM IRQs enabled at NVIC level */
nvicISER[wakeIdx] = NVIC->ISER[wakeIdx];
/* Clear unused system-level IRQs */
uint32_t maskVal = ~nvicISER[wakeIdx];
NVIC->ICPR[wakeIdx] = 0xFFFFFFFFU & maskVal;
/* Add system-level wake events */
maskVal &= sysWakeMask[wakeIdx];
/* Update GPC wake mask */
(void) CPU_IrqWakeSet(CPU_IDX_M33P, wakeIdx, maskVal);
/* Update NVIC wake mask */
NVIC->ICER[wakeIdx] = 0xFFFFFFFFU;
NVIC->ISER[wakeIdx] = ~maskVal;
}
/* Configure M33P to wake from GPC */
(void) CPU_WakeMuxSet(CPU_IDX_M33P, false);
/* Set target M33P sleep mode */
(void) CPU_SleepModeSet(CPU_IDX_M33P, sleepMode);
/* Extract and clamp performance level from system sleep mode */
uint32_t perfLevelSleep = (s_sysSleepMode & 0xF0U) >> 4U;
if (perfLevelSleep > DEV_SM_PERF_LVL_ODV)
{
perfLevelSleep = DEV_SM_PERF_LVL_ODV;
}
/* System remains active during sleep based on performance level
* and OSC24M configuration.
*/
bool activeSleep = (perfLevelSleep != DEV_SM_PERF_LVL_PRK) ||
((s_sysSleepFlags & DEV_SM_SSF_OSC24M_ACTIVE_MASK) != 0U) ||
lpComputeActive;
/* Check if OSC24M must remain active */
if (activeSleep)
{
/* Keep OSC_24M active during system sleep */
GPC_GLOBAL->GPC_ROSC_CTRL = 0U;
}
else
{
/* Shut off OSC_24M during system sleep */
GPC_GLOBAL->GPC_ROSC_CTRL =
GPC_GLOBAL_GPC_ROSC_CTRL_ROSC_OFF_EN_MASK;
}
/* Check PMIC_STBY system sleep mode flag */
if ((s_sysSleepFlags & DEV_SM_SSF_PMIC_STBY_INACTIVE_MASK) == 0U)
{
/* Enable GPC PMIC standby control */
GPC_GLOBAL->GPC_PMIC_CTRL =
GPC_GLOBAL_GPC_PMIC_CTRL_PMIC_STBY_EN_MASK;
}
else
{
/* Disable GPC PMIC standby control */
GPC_GLOBAL->GPC_PMIC_CTRL = 0U;
}
/* Power down eFUSE */
GPC_GLOBAL->GPC_EFUSE_CTRL =
GPC_GLOBAL_GPC_EFUSE_CTRL_EFUSE_PD_EN_MASK;
/* Disable bypass for clock sources */
DEV_SM_ClockSourceBypass(false, true);
if (activeSleep)
{
/* If staying active, move to system sleep performance level */
(void) DEV_SM_PerfSystemSleep(perfLevelSleep);
}
else
{
/* Notify ELE of suspend entry */
ELE_StartDvfsChange(ELE_DVFS_FLAG_SUSPEND, 0U, 0U, 0U);
/* Move ELE and SM clock roots to OSC_24M to allow SysPLL to be
* powered down. OSC_24M may be gated by hardware during final phases
* of system SUSPEND entry.
*/
for (uint32_t sleepRootIdx = 0U;
sleepRootIdx < DEV_SM_NUM_SLEEP_ROOTS;
sleepRootIdx++)
{
uint32_t rootIdx = s_clkRootSleepList[sleepRootIdx];
/* Save clock root context */
s_clkRootCtrl[sleepRootIdx] =
CCM_CTRL->CLOCK_ROOT[rootIdx].CLOCK_ROOT_CONTROL.RW;
/* Set MUX = 0 (OSC_24M) */
CCM_CTRL->CLOCK_ROOT[rootIdx].CLOCK_ROOT_CONTROL.CLR =
CCM_CLOCK_ROOT_MUX_MASK;
/* Set DIV = 0 (/1) */
CCM_CTRL->CLOCK_ROOT[rootIdx].CLOCK_ROOT_CONTROL.CLR =
CCM_CLOCK_ROOT_DIV_MASK;
}
}
/* Check if sleep performance level allows SYSPLL disable */
if (perfLevelSleep == DEV_SM_PERF_LVL_PRK)
{
/* Power down SYSPLL clock nodes */
uint32_t clkSrcIdx = CLOCK_SRC_SYSPLL1_PFD2_DIV2;
while (clkSrcIdx >= CLOCK_SRC_SYSPLL1_VCO)
{
(void) CLOCK_SourceSetEnable(clkSrcIdx, false);
clkSrcIdx--;
}
g_syslog.sysSleepRecord.pllPwrStat &= (~(1UL << CLOCK_PLL_SYS1));
}
/* Board-level sleep entry */
BOARD_SystemSleepEnter(s_sysSleepMode, s_sysSleepFlags);
/* Process SM LPIs for sleep entry */
(void) CPU_PerLpiProcess(CPU_IDX_M33P, sleepMode);
/* Check the expression values doesn't wrap */
if (DEV_SM_Usec64Get() >= sleepEntryStart)
{
/* Capture sleep entry latency */
g_syslog.sysSleepRecord.sleepEntryUsec =
UINT64_L(DEV_SM_Usec64Get() - sleepEntryStart);
}
else
{
/* Initialize to zero in case of wrap */
g_syslog.sysSleepRecord.sleepEntryUsec = 0U;
}
/* Check SYSCTR system sleep mode flag */
if ((s_sysSleepFlags & DEV_SM_SSF_SYSCTR_ACTIVE_MASK) != 0U)
{
/* Switch SYSCTR to low-freq mode (blocking) */
SYSCTR_FreqMode(true, true);
}
/* Manage FRO based on system sleep flags and active sleep state */
if (((s_sysSleepFlags & DEV_SM_SSF_FRO_ACTIVE_MASK) == 0U) &&
!activeSleep)
{
/* Power down FRO */
FRO->CSR.CLR = FRO_CSR_FROEN_MASK;
}
/* Enter WFI to trigger sleep entry */
__DSB();
/* coverity[misra_c_2012_rule_1_2_violation] */
__WFI();
__ISB();
/* Power up FRO */
FRO->CSR.SET = FRO_CSR_FROEN_MASK;
/* Check SYSCTR system sleep mode flag
*
* NOTE: switch completion required before read of exit timestamp
*/
if ((s_sysSleepFlags & DEV_SM_SSF_SYSCTR_ACTIVE_MASK) != 0U)
{
/* Switch SYSCTR to high-freq mode (blocking) */
SYSCTR_FreqMode(false, true);
}
/* Capture start of sleep exit */
sleepExitStart = DEV_SM_Usec64Get();
/* Capture wake source */
g_syslog.sysSleepRecord.wakeSource =
(SCB->ICSR & SCB_ICSR_VECTPENDING_Msk)
>> SCB_ICSR_VECTPENDING_Pos;
/* Process SM LPIs for sleep exit */
(void) CPU_PerLpiProcess(CPU_IDX_M33P, CPU_SLEEP_MODE_RUN);
/* Board-level sleep exit */
BOARD_SystemSleepExit(s_sysSleepMode, s_sysSleepFlags);
/* Check if sleep performance level requires SYSPLL enable */
if (perfLevelSleep == DEV_SM_PERF_LVL_PRK)
{
/* Power up SYSPLL clock nodes */
uint32_t clkSrcIdx = CLOCK_SRC_SYSPLL1_VCO;
while (clkSrcIdx <= CLOCK_SRC_SYSPLL1_PFD2_DIV2)
{
(void) CLOCK_SourceSetEnable(clkSrcIdx, true);
clkSrcIdx++;
}
}
if (activeSleep)
{
/* Move to system wake performance level */
(void) DEV_SM_PerfSystemWake(perfLevelSleep);
}
else
{
/* Restore ELE and SM clock roots */
for (uint32_t sleepRootIdx = 0U;
sleepRootIdx < DEV_SM_NUM_SLEEP_ROOTS;
sleepRootIdx++)
{
uint32_t rootIdx = s_clkRootSleepList[sleepRootIdx];
/* Restore DIV */
CCM_CTRL->CLOCK_ROOT[rootIdx].CLOCK_ROOT_CONTROL.SET =
s_clkRootCtrl[sleepRootIdx] & CCM_CLOCK_ROOT_DIV_MASK;
/* Restore MUX */
CCM_CTRL->CLOCK_ROOT[rootIdx].CLOCK_ROOT_CONTROL.SET =
s_clkRootCtrl[sleepRootIdx] & CCM_CLOCK_ROOT_MUX_MASK;
}
/* Notify ELE of suspend exit */
ELE_StopDvfsChange();
}