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# SM configuration file for the MX95 EVK
MAKE soc=MIMX95, board=mcimx95evk, build=gcc_cross
DOX name=MX95EVK, desc="i.MX95 EVK Configuration Data"
include ../devices/MIMX95/configtool/device.cfg
#==========================================================================#
# Board #
#==========================================================================#
BOARD DEBUG_UART_INSTANCE=2
BOARD DEBUG_UART_BAUDRATE=115200
BOARD I2C_INSTANCE=1
BOARD I2C_BAUDRATE=400000
#==========================================================================#
# Common Defines #
#==========================================================================#
NOTIFY: api=notify
GET: api=get
SET: api=set
PRIV: api=priv
ALL: api=all
READONLY: perm=ro
#==========================================================================#
# ELE Domain #
#==========================================================================#
DOM0 name="ELE", did=0
OWNER: perm=sec_rw, api=all
ACCESS: perm=sec_rw, api=none, mdid=none
DATA: perm=rw
# Resources
# Sharing MP access may not be safe if FuSa SW using EDMA2
EDMA2_MP ACCESS
EDMA2_CH0_1 OWNER
V2X_ACC OWNER
# Memory
M33_TCM_SYS DATA, begin=0x020200000, size=256K
OCRAM DATA, begin=0x020480000, size=352K
DDR DATA, begin=0x080000000, end=0x87FFFFFFF, nodbg
#==========================================================================#
# ISP Domain #
#==========================================================================#
DOM10 name="ISP", did=10
OWNER: perm=rw
#==========================================================================#
# V2X Domain #
#==========================================================================#
DOM12 name="V2X", did=12
DFMT1: sa=bypass, pa=bypass
OWNER:
# Resources
V2X_FH OWNER
# Memory
DDR READONLY, begin=0x080000000, end=0x08AFFFFFF, nodbg
DDR DATA, begin=0x08B000000, end=0x08BFFFFFF, nodbg
DDR READONLY, begin=0x08C000000, end=0x87FFFFFFF, nodbg
#==========================================================================#
# SM M33 EENV #
#==========================================================================#
LM0 name="SM", rpc=none, boot=1, did=2, safe=feenv
DFMT0: sa=secure
DFMT1: sa=secure, pa=privileged
OWNER: perm=sec_rw, api=all
ACCESS: perm=sec_rw, api=none, mdid=none
TEST_MU: perm=sec_rw
EXEC: perm=sec_rwx
DATA: perm=sec_rw
MODE msel=1, boot=1
MODE msel=2, boot=1
#==========================================================================#
# M7 EENV #
#==========================================================================#
LM1 name="M7", rpc=scmi, boot=2, skip=1, did=4, safe=seenv
DFMT0: sa=secure
DFMT1: sa=secure, pa=privileged
OWNER: perm=rw, api=all
EXEC: perm=full
DATA: perm=rw
# Start/Stop (mSel=0)
PD_M7 start=1, stop=2
CPU_M7P start=2, stop=1
# Start/Stop (mSel=1)
MODE msel=1, boot=2
PD_M7 msel=1, start=1, stop=2
CPU_M7P msel=1, start=2, stop=1
# Start/Stop (mSel=2)
PD_M7 msel=2, start=1, stop=2
CPU_M7P msel=2, start=2, stop=1
# RPC Interface
SCMI_AGENT0 name="M7"
MAILBOX type=mu, mu=9, test=8, priority=high
CHANNEL db=0, xport=smt, check=crc32, rpc=scmi, type=a2p, \
test=default
CHANNEL db=1, xport=smt, check=crc32, rpc=scmi, \
type=p2a_notify, notify=24
CHANNEL db=2, xport=smt, check=crc32, rpc=scmi, \
type=p2a_priority
#==========================================================================#
# A55 secure EENV #
#==========================================================================#
LM2 name="AP", rpc=scmi, boot=3, skip=1, did=3, default
DFMT0: sa=bypass
DFMT1: sa=secure, pa=privileged
OWNER: perm=sec_rw, api=all
EXEC: perm=sec_rwx
DATA: perm=sec_rw
# Start/Stop (mSel=0)
VOLT_ARM start=1|1, stop=9
PD_A55P start=2, stop=8, test
PD_A55C0 stop=7
PD_A55C1 stop=6
PD_A55C2 stop=5
PD_A55C3 stop=4
PD_A55C4 stop=3
PD_A55C5 stop=2
PERF_A55 start=3|3
CPU_A55C0 start=4
CPU_A55P stop=1
# Start/Stop (mSel=1)
VOLT_ARM msel=1, start=1|1, stop=9
PD_A55P msel=1, start=2, stop=8
PD_A55C0 msel=1, stop=7
PD_A55C1 msel=1, stop=6
PD_A55C2 msel=1, stop=5
PD_A55C3 msel=1, stop=4
PD_A55C4 msel=1, stop=3
PD_A55C5 msel=1, stop=2
PERF_A55 msel=1, start=3|3
CPU_A55C0 msel=1, start=4
CPU_A55P msel=1, stop=1
# Start/Stop (mSel=2)
VOLT_ARM msel=2, start=1|1, stop=9
PD_A55P msel=2, start=2, stop=8
PD_A55C0 msel=2, stop=7
PD_A55C1 msel=2, stop=6
PD_A55C2 msel=2, stop=5
PD_A55C3 msel=2, stop=4
PD_A55C4 msel=2, stop=3
PD_A55C5 msel=2, stop=2
PERF_A55 msel=2, start=3|3
CPU_A55C0 msel=2, start=4
CPU_A55P msel=2, stop=1
# RPC Interface
SCMI_AGENT1 name="AP-S", secure
MAILBOX type=mu, mu=1, test=0
CHANNEL db=0, xport=smt, rpc=scmi, type=a2p
CHANNEL db=1, xport=smt, rpc=scmi, type=p2a_notify
#==========================================================================#
# A55 non-secure EENV #
#==========================================================================#
DFMT0: sa=nonsecure
DFMT1: sa=nonsecure, pa=privileged
OWNER: perm=rw, api=all
ACCESS: perm=rw, api=all, mdid=none
EXEC: perm=full
DATA: perm=rw
# RPC Interface
SCMI_AGENT2 name="AP-NS"
MAILBOX type=mu, mu=3, test=2
CHANNEL db=0, xport=smt, rpc=scmi, type=a2p
CHANNEL db=1, xport=smt, rpc=scmi, type=p2a_notify
Функция main system manager (M33)
int main(int argc, const char * const argv[])
{
int32_t status = SM_ERR_SUCCESS;
uint64_t delta;
uint32_t mSel = 0U;
/* Store boot start time */
g_bootTime[SM_BT_START] = DEV_SM_Usec64Get();
/* Init the system hardware */
status = BRD_SM_Init(argc, argv, &mSel);
/* Save start banner time */
delta = DEV_SM_Usec64Get();
/* Print banner */
printf("\nHello from SM (Build %lu, Commit %08lx, %s %s)\n\n",
SM_BUILD, SM_COMMIT, SM_DATE, SM_TIME);
/* Add to subtract time */
/* Intentional: used only for debug */
/* coverity[cert_int30_c_violation] */
g_bootTime[SM_BT_SUB] += (DEV_SM_Usec64Get() - delta);
/* Init LMM */
if (status == SM_ERR_SUCCESS)
{
/* mSel from BRD_SM_Init(), LMM_INIT_FLAGS from Makefile */
status = LMM_Init(&mSel, LMM_INIT_FLAGS);
}
#ifndef SIMU
/* Start systick, disable boot WDOG */
SM_SYSTICKENABLE();
#endif
if (status == SM_ERR_SUCCESS)
{
/* Mark LMM inited */
s_lmmInited = true;
/* Boot LMs */
status = LMM_Boot();
}
/* Post-boot cleanup */
if (status == SM_ERR_SUCCESS)
{
status = LMM_PostBoot();
}
...
return status;
}
int32_t LMM_CpuInit(void)
{
int32_t status = SM_ERR_SUCCESS;
/* Loop over CPUs */
for (uint32_t cpuId = 0U; cpuId < SM_NUM_CPU; cpuId++)
{
uint32_t mSel;
uint32_t flags;
/* Get boot data */
if (DEV_SM_RomBootCpuGet(cpuId, &s_bootVector[cpuId], &mSel,
&flags) == SM_ERR_SUCCESS)
{
/* Save ROM provided vector */
s_bootFlags[cpuId] = true;
}
else
{
s_bootFlags[cpuId] = false;
}
}
/* Return status */
return status;
}
int32_t LMM_Boot(void)
{
int32_t status;
uint32_t mSel = s_mSel;
uint32_t lmmInitFlags = s_lmmInitFlags;
/* Default out of range mSel */
if (mSel >= SM_LM_NUM_MSEL)
{
mSel = 0U;
}
/* Inform LM system of mode select */
status = LMM_SystemModeSelSet(mSel);
/* Get starting system counter */
uint64_t startTime = DEV_SM_Usec64Get();
/* Boot LMs */
if ((status == SM_ERR_SUCCESS)
&& ((lmmInitFlags & LM_INIT_FLAGS_BOOT) != 0U))
{
/* Loop over boot order */
for (uint8_t bootOrder = 1U; bootOrder <= SM_NUM_LM; bootOrder++)
{
/* Loop over LMs */
for (uint32_t lmId = 0U; lmId < SM_NUM_LM; lmId++)
{
/* Boot if LM requested in this order */
if (g_lmmConfig[lmId].boot[mSel] == bootOrder)
{
uint64_t bootTime = startTime
+ ((uint64_t) g_lmmConfig[lmId].rtime);
/* Wait until start time */
while (DEV_SM_Usec64Get() < bootTime)
{
; /* Intentional empty while */
}
/* Record calling parms */
s_bootLm = lmId;
s_bootSkip = g_lmmConfig[lmId].bootSkip[mSel];
/* Trigger SWI handler */
SWI_Trigger();
/* Collect status */
status = s_bootStatus;
}
/* Exit loop on error */
if (status != SM_ERR_SUCCESS)
{
break;
}
}
/* Exit loop on error */
if (status != SM_ERR_SUCCESS)
{
break;
}
}
}
/* Return status */
return status;
}
