https://pastein.ru/t/nNB
Загрузка данных
/*--------------------------------------------------------------------------*/
/* Sleep the system */
/*--------------------------------------------------------------------------*/
int32_t DEV_SM_SystemSleep(uint32_t sleepMode)
{
static const uint32_t s_clkRootSleepList[DEV_SM_NUM_SLEEP_ROOTS] =
{
[0] = CLOCK_ROOT_ELE,
[1] = CLOCK_ROOT_BUSAON,
[2] = CLOCK_ROOT_M33
};
static const uint32_t s_pllVcoList[CLOCK_NUM_PLL] =
{
[CLOCK_PLL_SYS1] = CLOCK_SRC_SYSPLL1_VCO,
[CLOCK_PLL_AUDIO1] = CLOCK_SRC_AUDIOPLL1_VCO,
[CLOCK_PLL_AUDIO2] = CLOCK_SRC_AUDIOPLL2_VCO,
[CLOCK_PLL_VIDEO1] = CLOCK_SRC_VIDEOPLL1_VCO,
[CLOCK_PLL_ARM] = CLOCK_SRC_ARMPLL_VCO,
[CLOCK_PLL_DRAM] = CLOCK_SRC_DRAMPLL_VCO,
[CLOCK_PLL_HSIO] = CLOCK_SRC_HSIOPLL_VCO,
[CLOCK_PLL_LDB] = CLOCK_SRC_LDBPLL_VCO
};
static src_mem_slice_t const *const s_srcMemPtrs[] = SRC_MEM_BASE_PTRS;
int32_t status = SM_ERR_SUCCESS;
uint32_t s_clkRootCtrl[DEV_SM_NUM_SLEEP_ROOTS];
uint32_t cpuWakeMask[CPU_NUM_IDX][GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT];
uint32_t sysWakeMask[GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT];
uint32_t nvicISER[GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT];
/* Capture start of sleep entry */
uint64_t sleepEntryStart = DEV_SM_Usec64Get();
uint64_t sleepExitStart = sleepEntryStart;
/* Reset wake source of sleep record */
g_syslog.sysSleepRecord.wakeSource = 0U;
/* Capture system sleep mode/flags */
g_syslog.sysSleepRecord.sysSleepMode = s_sysSleepMode;
g_syslog.sysSleepRecord.sysSleepFlags = s_sysSleepFlags;
/* Capture power status of MIXes */
g_syslog.sysSleepRecord.mixPwrStat = 0U;
for (uint32_t mixIdx = 0U; mixIdx < PWR_NUM_MIX_SLICE; mixIdx++)
{
if (SRC_MixIsPwrSwitchOn(mixIdx))
{
g_syslog.sysSleepRecord.mixPwrStat |= (1UL << mixIdx);
}
}
/* Capture power status of memories */
g_syslog.sysSleepRecord.memPwrStat = 0U;
for (uint32_t memIdx = 0U; memIdx < PWR_NUM_MEM_SLICE; memIdx++)
{
const src_mem_slice_t *srcMem = s_srcMemPtrs[memIdx];
if ((srcMem->MEM_CTRL & SRC_MEM_MEM_CTRL_MEM_LP_MODE_MASK) != 0U)
{
g_syslog.sysSleepRecord.memPwrStat |= (1UL << memIdx);
}
}
/* Capture power status of PLLs */
g_syslog.sysSleepRecord.pllPwrStat = 0U;
for (uint32_t pllIdx = 0U; pllIdx < CLOCK_NUM_PLL; pllIdx++)
{
uint32_t sourceIdx = s_pllVcoList[pllIdx];
if (CLOCK_SourceGetEnable(sourceIdx))
{
g_syslog.sysSleepRecord.pllPwrStat |= (1UL << pllIdx);
}
}
/* Initialize wake masks */
for (uint32_t wakeIdx = 0;
wakeIdx < GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT;
wakeIdx++)
{
sysWakeMask[wakeIdx] = 0xFFFFFFFFU;
for (uint32_t cpuIdx = 0U; cpuIdx < CPU_NUM_IDX; cpuIdx++)
{
cpuWakeMask[cpuIdx][wakeIdx] = 0xFFFFFFFFU;
}
}
/* Initialize NOC/WAKEUP MIX dependencies */
uint32_t lpmSettingNoc = CPU_PD_LPM_ON_NEVER;
uint32_t lpmSettingWakeup = CPU_PD_LPM_ON_NEVER;
/* Scan CPUs, update GPC wake masks, assess NOC/WAKEUP MIX dependencies */
for (uint32_t cpuIdx = 0U; cpuIdx < CPU_NUM_IDX; cpuIdx++)
{
if (cpuIdx != CPU_IDX_M33P)
{
/* Check if sleep is forced for the CPU */
bool sleepForce;
if (CPU_SleepForceGet(cpuIdx, &sleepForce))
{
/* If sleep is not forced, manage GPC masks */
if (!sleepForce)
{
/* IRQs enabled at NVIC level become GPC wake sources */
for (uint32_t wakeIdx = 0;
wakeIdx < GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT;
wakeIdx++)
{
uint32_t wakeVal;
if (CPU_IrqWakeGet(cpuIdx, wakeIdx, &wakeVal))
{
cpuWakeMask[cpuIdx][wakeIdx] = wakeVal;
sysWakeMask[wakeIdx] &= wakeVal;
(void) CPU_IrqWakeSet(cpuIdx, wakeIdx,
0xFFFFFFFFU);
}
}
/* Update NOCMIX dependency */
uint32_t lpmSetting;
if (SRC_MixCpuLpmGet(PWR_MIX_SLICE_IDX_NOC, cpuIdx,
&lpmSetting))
{
if (lpmSetting > lpmSettingNoc)
{
lpmSettingNoc = lpmSetting;
}
}
/* Update WAKEUPMIX dependency */
if (SRC_MixCpuLpmGet(PWR_MIX_SLICE_IDX_WAKEUP, cpuIdx,
&lpmSetting))
{
if (lpmSetting > lpmSettingWakeup)
{
lpmSettingWakeup = lpmSetting;
}
}
}
/* Disable GPC wakeups for CPUs forced to sleep */
else
{
/* IRQs enabled at NVIC level become GPC wake sources */
for (uint32_t wakeIdx = 0;
wakeIdx < GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT;
wakeIdx++)
{
uint32_t wakeVal;
if (CPU_IrqWakeGet(cpuIdx, wakeIdx, &wakeVal))
{
cpuWakeMask[cpuIdx][wakeIdx] = wakeVal;
(void) CPU_IrqWakeSet(cpuIdx, wakeIdx,
0xFFFFFFFFU);
}
}
}
}
}
}
/* Check system sleep status after clearing GPC masks */
uint32_t sysSleepStat;
if (CPU_SystemSleepStatusGet(&sysSleepStat))
{
/* If system can sleep after clearing GPC masks, SUSPEND
* processing has reached point of coherency. Agent CPUs
* cannot wake without SM completion of SUSPEND entry/exit
* sequence below.
*/
if (sysSleepStat == CPU_SLEEP_MODE_SUSPEND)
{
/* Board-level sleep prepare */
BOARD_SystemSleepPrepare(s_sysSleepMode, s_sysSleepFlags);
/* Disable sensor */
(void) DEV_SM_SensorPowerDown(DEV_SM_SENSOR_TEMP_ANA);
/* Check the value doesn't wrap */
if (g_syslog.sysSleepRecord.sleepCnt <= (UINT32_MAX - 1U))
{
/*! Increment system sleep counter */
g_syslog.sysSleepRecord.sleepCnt++;
}
else
{
/* Initialize to zero in case of wrap */
g_syslog.sysSleepRecord.sleepCnt = 0U;
}
bool ddrInRetention = false;
/* Limit DDR access path to SM */
if (DEV_SM_RdcDdrBlock(true) == SM_ERR_SUCCESS)
{
/* Attempt to place DDR into retention */
if (DEV_SM_MemDdrRetentionEnter() == SM_ERR_SUCCESS)
{
/* Set flag to indicate DDR retention is active */
ddrInRetention = true;
/* Power down DDRMIX */
if (DEV_SM_PowerStateSet(DEV_SM_PD_DDR, DEV_SM_POWER_STATE_OFF)
== SM_ERR_SUCCESS)
{
g_syslog.sysSleepRecord.mixPwrStat &=
(~(1UL << PWR_MIX_SLICE_IDX_DDR));
}
}
}
/* If NOCMIX powered down during SUSPEND, force power down */
if (lpmSettingNoc <= sleepMode)
{
if (DEV_SM_PowerStateSet(DEV_SM_PD_NOC, DEV_SM_POWER_STATE_OFF)
== SM_ERR_SUCCESS)
{
g_syslog.sysSleepRecord.mixPwrStat &=
(~(1UL << PWR_MIX_SLICE_IDX_NOC));
}
}
/* Query if any CPU in LP compute mode */
bool lpComputeActive = (CPU_LpComputeListGet() != 0U);
/* Track if WAKEUPMIX powered down */
bool wakeupMixOff = false;
/* Track if WAKEUPMIX performance level forced */
bool restoreWakeupMixPerf = false;
uint32_t savedWakeupMixPerf;
/* If WAKEUPMIX powered down during SUSPEND, force power down */
if ((lpmSettingWakeup <= sleepMode) &&
((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == 0x0U))
{
/* Keep WAKEUPMIX powered at parked level during LP compute */
if (lpComputeActive)
{
if (DEV_SM_PerfLevelGet(DEV_SM_PERF_WAKEUP,
&savedWakeupMixPerf) == SM_ERR_SUCCESS)
{
if (DEV_SM_PerfLevelSet(DEV_SM_PERF_WAKEUP,
DEV_SM_PERF_LVL_PRK) == SM_ERR_SUCCESS)
{
restoreWakeupMixPerf = true;
}
}
}
else
{
if (DEV_SM_PowerStateSet(DEV_SM_PD_WAKEUP,
DEV_SM_POWER_STATE_OFF) == SM_ERR_SUCCESS)
{
g_syslog.sysSleepRecord.mixPwrStat &=
(~(1UL << PWR_MIX_SLICE_IDX_WAKEUP));
wakeupMixOff = true;
}
}
}
