---

#include "fsl_device_registers.h"
#include "fsl_debug_console.h"
#include "board.h"
#include "app.h"

#include <stdint.h>
#include <stddef.h>
#include <string.h>

#define IPC_MAGIC_M7_READY    0x4D37424CU  /* "M7BL" - Set by M7 to signal it has booted and cleared RAM */
#define IPC_MAGIC_UB_READY    0x55424D37U  /* "UBM7" - Set by U-Boot to open a legitimate transfer session */
#define DTCM_DATA_BUFFER_SIZE 204800

struct rproc_update_ipc {
    uint32_t magic_word;
    uint32_t command;       /* Command from U-Boot: 1=DATA_READY, 2=VERIFY_CRC */
    uint32_t status;        /* Status from M7: 0=IDLE, 1=BUSY, 2=ACK, 3=ERROR */
    uint32_t chunk_size;    /* Current chunk size in bytes */
    uint32_t target_ddr;    /* Current target write offset in DDR */
    uint32_t expected_crc;  /* Reference total CRC32 of the entire image */
    uint8_t  buffer[DTCM_DATA_BUFFER_SIZE];/* Data buffer located in M7 TCM (200 KB) */
};

#define IPC_DTCM_OFFSET 0xDFE4 /*DTCM offset from begin for IPC */
#define IPC_BASE_ADDR   0x20000000 /* Local start address of DTCM for M7*/
#define CMD_DATA_READY  1U
#define CMD_VERIFY_CRC  2U

#define STAT_IDLE       0U
#define STAT_BUSY       1U
#define STAT_ACK        2U
#define STAT_ERROR      3U

/* Standard IEEE 802.3 CRC32 Lookup Table (Matches U-Boot / Linux / zlib) */
static const uint32_t crc32_table[256] = {
    0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
    0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97DCD988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
    0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
    0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC, 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
    0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172, 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
    0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940, 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
    0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116, 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
    0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924, 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
    0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A, 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
    0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818, 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
    0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E, 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
    0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C, 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
    0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2, 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
    0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0, 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
    0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086, 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
    0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4, 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
    0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A, 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
    0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8, 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
    0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE, 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
    0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC, 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
    0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252, 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
    0xD80180E8, 0xAF06B07E, 0x360FE1C4, 0x4108D152, 0xDF6C40F1, 0xA86B7067, 0x316221DD, 0x4665114B,
    0xCC011047, 0xBB0620D1, 0x220F716B, 0x550841FD, 0xC56CC45E, 0xB26BF4C8, 0x2B62A572, 0x5C6595E4,
    0xC2077D55, 0xB5004DC3, 0x2C091C79, 0x5B0E2CEF, 0x857F246C, 0xFD0154FA, 0x7161F422, 0x0666C4B4,
    0x4A616254, 0x3D6652C2, 0xA46F0378, 0xD36833EE, 0x4D0C26FD, 0x3A0B166B, 0xA30247D1, 0xD4057747,
    0x446A316E, 0x336D01F8, 0xAA645042, 0xDD6360D4, 0x430732E7, 0x34010271, 0xAB0913CB, 0xDC0E235D,
    0x57616254, 0x206652C2, 0xB96F0378, 0xCE6833EE, 0x500C26FD, 0x270B166B, 0xBE0247D1, 0xC9057747,
    0x596A316E, 0x2E6D01F8, 0xB7645042, 0xC06360D4, 0x5E0732E7, 0x29010271, 0xB00913CB, 0xC70E235D,
    0x3F616254, 0x486652C2, 0xD16F0378, 0xA66833EE, 0x380C26FD, 0x4F0B166B, 0xD60247D1, 0xA1057747,
    0x316A316E, 0x466D01F8, 0xDF645042, 0xA86360D4, 0x360732E7, 0x41010271, 0xDA0913CB, 0xAD0E235D,
    0x2E616254, 0x596652C2, 0xC06F0378, 0xB76833EE, 0x290C26FD, 0x5E0B166B, 0xC70247D1, 0xB0057747,
    0x236A316E, 0x546D01F8, 0xCD645042, 0xBA6360D4, 0x240732E7, 0x53010271, 0xCA0913CB, 0xBD0E235D
};

/**
 * @brief Fast stream-based CRC32 calculation.
 *        100% compatible with U-Boot standard 'crc32' command.
 * @param crc Previous accumulated CRC value
 * @param buf Pointer to the data chunk buffer.
 * @param len Size of the chunk in bytes.
 * @return Updated CRC32 value.
 */
uint32_t calculate_crc32(uint32_t crc, const uint8_t *buf, uint32_t len)
{
    while (len--) {
        crc = (crc >> 8) ^ crc32_table[(crc ^ *buf++) & 0xFF];
    }
    return crc;
}

void tcm_bootloader_main(void)
{
    /* Mapping IPC structure onto DTCM memory region */
    struct rproc_update_ipc *ipc = (struct rproc_update_ipc *)(IPC_BASE_ADDR + IPC_DTCM_OFFSET);
    uint32_t current_ddr_ptr = 0x80000000U;       /* Target execution DDR memory address for M7 */
    uint32_t calculated_total_crc; /* Standard CRC32 initializtion vector */

    //memset((void *)ipc, 0, offsetof(struct rproc_update_ipc, buffer));
    /* Clean initial state */
    ipc->magic_word = IPC_MAGIC_M7_READY;
    ipc->command = 0;
    ipc->status = STAT_IDLE;

    PRINTF("Wait U-BOOT magic_word 0x%X\r\n",IPC_MAGIC_UB_READY);
    while(ipc->magic_word != IPC_MAGIC_UB_READY) {
            __NOP();
            __NOP();
    }
    PRINTF("U-BOOT magic_word 0x%X become success\r\n",IPC_MAGIC_UB_READY);
    calculated_total_crc = 0xFFFFFFFFU;
    while(1) {
        /* Force volatile read of the command flag to prevent compiler optimization loops */
        uint32_t cmd = *(volatile uint32_t *)&(ipc->command);

        if(ipc->magic_word != IPC_MAGIC_UB_READY) {
            ipc->status = STAT_ERROR;
            break;
        }

        if (cmd == CMD_DATA_READY) {
            PRINTF("Have CMD_DATA_READY from U-BOOT\r\n");
            ipc->status = STAT_BUSY;
            __DSB(); /* Ensure status write completes before processing data */
            /* Safe memory block copy from TCM communication buffer to target DDR location */
            memcpy((void *)current_ddr_ptr, (const void *)ipc->buffer, ipc->chunk_size);
            /* Feed the chunk into the continuous stream CRC32 accumulator */
            calculated_total_crc = calculate_crc32(calculated_total_crc, (const uint8_t *)ipc->buffer, ipc->chunk_size);
            
            /* Advance the DDR pointer forward by the size of the written chunk */
            current_ddr_ptr += ipc->chunk_size;
            
            /* Data Synchronization Barrier: Ensure all bus transaction write cycles to DDR are complete */
            __DSB(); __ISB();

            /* Signal U-Boot that the data chunk has been acknowledged and saved */
            ipc->command = 0;
            ipc->status = STAT_ACK;
            __DSB();
        } 
        else if (cmd == CMD_VERIFY_CRC) {
            PRINTF("Have CMD_VERIFY_CRC from U-BOOT\r\n");
            ipc->status = STAT_BUSY;
            __DSB();
            calculated_total_crc = calculated_total_crc ^ 0xFFFFFFFFU;
            if (calculated_total_crc == ipc->expected_crc) {
                PRINTF("CRC is ok\r\n");
                /* Flush and clean Data Cache for the loaded firmware region in DDR */
                SCB_CleanDCache_by_Addr((void *)0x80000000U, (current_ddr_ptr - 0x80000000U));
                /* Invalidate Instruction Cache to force CPU reload instructions from modified DDR memory */
                SCB_InvalidateICache();
                __DSB();
                __ISB();
#if 0
                /* Fetch the entry point address (Reset Handler) from the Application Vector Table */
                uint32_t jump_address = *(volatile uint32_t *)(0x80000004U);

                /* CRITICAL FOR CORTEX-M: Force the least significant bit (LSB) to 1.
                   This signals the ARM core to enter Thumb-2 state execution mode, preventing HardFaults. */
                jump_address |= 1U; 
                
                void (*entry_point)(void) = (void (*)(void))jump_address;

                /* Respond to the host with final ACK status before relinquishing control */
                ipc->command = 0;
                ipc->status = STAT_ACK;
                __DSB(); __ISB();

                /* Relocate Vector Table Offset Register (VTOR) to point to the base of DDR application */
                SCB->VTOR = 0x80000000U;

                /* Load Main Stack Pointer (MSP) from the very first word of the firmware binary */
                __set_MSP(*(volatile uint32_t *)(0x80000000U));
                
                /* Branch execution context directly to the application entry point */
                entry_point();
#else
                /* Respond to the host with final ACK status before relinquishing control */
                ipc->command = 0;
                ipc->status = STAT_ACK;
                __DSB(); __ISB();

                PRINTF("Try start M7 from DDR\r\n");
                while(1) {
                    __NOP();
                    __NOP();
                };
#endif
            } else {
                /* CRC Mismatch Error state handling */
                PRINTF("CRC Mismatch Error 0x%X != 0x%X\r\n",calculated_total_crc,ipc->expected_crc);
                ipc->command = 0;
                ipc->status = STAT_ERROR;
                __DSB();

                /* Reset internal tracking states to allow recovery or retry firmware transmission */
                calculated_total_crc = 0xFFFFFFFFU;
                current_ddr_ptr = 0x80000000U;
            }
        }
        else {
            /* Low-Power Optimization for Bare-metal: 
               Puts the Cortex-M7 core into sleep state until any hardware interrupt occurs 
               (e.g., Systick, MU Mailbox, or Timer interrupt). Prevents pinning the CPU to 100%. */
            __NOP();
            __NOP(); 
        }
    }
    return;
}

/*!
 * @brief Main function
 */
int main(void)
{
    /* Init board hardware. */
    BOARD_InitHardware();
    PRINTF("MCUX SDK version: %s\r\n", MCUXSDK_VERSION_FULL_STR);
    PRINTF("Bootloader.\r\n");
#if 0
    tcm_bootloader_main();
#else
    char ch;
    while (1)
    {
        ch = GETCHAR();
        PUTCHAR(ch);
    }
#endif
}