---

module UserLogic(
    input clk_i,
    input nrst_i,
    input data_i,
    output reg trig_o);
    
    localparam S_IDLE = 2'b00,
               S_ONE  = 2'b01,
               S_ZERO = 2'b10,
               S_DONE = 2'b11;
               
    reg [1:0] state, next_state;
    
    // Регистр состояния
    always @(posedge clk_i or negedge nrst_i) begin
        if (!nrst_i)
            state <= S_IDLE;
        else
            state <= next_state;
    end
    
    // Логика выходов
     always @(posedge clk_i or negedge nrst_i) begin
        if (!nrst_i)begin
            trig_o <= 1'b0;
        end else begin
            if (next_state == S_DONE)
                trig_o = 1'b1;
            else
                trig_o = 1'b0;
        end
    end
    
    // Логика переходов
    always @(*) begin
        case(state)
            S_IDLE: next_state = data_i ? S_ONE : S_IDLE;
            S_ONE:  next_state = data_i ? S_ONE : S_ZERO;
            S_ZERO: next_state = data_i ? S_DONE : S_IDLE;
            S_DONE: next_state = data_i ? S_ONE : S_ZERO;
            default: next_state = S_IDLE;
        endcase
    end
endmodule




`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 04.05.2026 17:23:33
// Design Name: 
// Module Name: UserLogic_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module UserLogic_tb();
    reg clk;
    reg reset;
    reg in_data;
    wire out_data;
    
    UserLogic DUT (
        .clk_i(clk),
        .nrst_i(reset),
        .data_i(in_data),
        .trig_o(out_data));
    always #5 clk = ~clk;
    initial begin
        clk = 0;
        reset = 0;
        in_data = 0;
        
        //Сброс системы
        #20 reset = 1;
        
        #1000 $finish;
    end
    
    always @(posedge clk) begin
        in_data <= $random;
    end
    
    //Мониторинг в консоли
    initial begin
        $monitor("Time=%0t | State=%b | Next_State=%b | In=%b | Out=%b",
                    $time, DUT.state, DUT.next_state, in_data, out_data);
    end
endmodule