---

module UserLogic(
    input clk_i,
    input nrst_i,
    input data_i,
    output reg trig_o);
    
    localparam S_IDLE = 3'b000,
               S_1  = 3'b001,
               S_10 = 3'b010,
               S_100 = 3'b011,
               S_1001= 3'b100,
               S_10011 = 3'b101,
               S_100111 = 3'b110;
               
    reg [2:0] state, next_state;
    
    // Регистр состояния
    always @(posedge clk_i or negedge nrst_i) begin
        if (!nrst_i)
            state <= S_IDLE;
        else
            state <= next_state;
    end
    
    // Логика выходов
     always @(posedge clk_i or negedge nrst_i) begin
        if (!nrst_i)begin
            trig_o <= 1'b0;
        end else begin
            if (next_state == S_100111)
                trig_o = 1'b1;
            else
                trig_o = 1'b0;
        end
    end
    
    // Логика переходов
    always @(*) begin
        case(state)
            S_IDLE: next_state = data_i ? S_IDLE : S_1;
            S_1: next_state = data_i ? S_1  : S_10;
            S_10:  next_state = data_i ? S_IDLE : S_100;
            S_100: next_state = data_i ? S_1001 : S_IDLE;
            S_1001: next_state = data_i ? S_10011 : S_10;
            S_10011: next_state = data_i ? S_100111 : S_10;
            S_100111: next_state = data_i ? S_1 : S_10;
            default: next_state = S_IDLE;
        endcase
    end
endmodule