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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity clk_deb is
port (
clk : in std_logic;
clk_debug: out std_logic
);
end entity;
architecture rtl of clk_deb is
signal counter : integer := 0;
signal clk_temp: std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if counter = 5000000 then
counter <= 0;
clk_temp <= not clk_temp;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_debug <= clk_temp;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity timer is
generic (
MAX_COUNT : integer := 10000000 -- ПАРАМЕТР ЗДЕСЬ
);
port (
clk : in std_logic;
tick : out std_logic
);
end entity;
architecture rtl of timer is
signal counter : integer := 0;
signal tick_s : std_logic := '0';
begin
process(clk)
begin
if rising_edge(clk) then
if counter >= MAX_COUNT - 1 then
counter <= 0;
tick_s <= '1';
else
counter <= counter + 1;
tick_s <= '0';
end if;
end if;
end process;
tick <= tick_s;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
entity pos_controll is
port (
clk : in std_logic;
tick : in std_logic;
position : out integer range 0 to 15
);
end entity;
architecture rtl of pos_controll is
signal pos : integer range 0 to 15 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if tick = '1' then
if pos = 15 then
pos <= 0;
else
pos <= pos + 1;
end if;
end if;
end if;
end process;
position <= pos;
end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity calc is
port (
clk : in STD_LOGIC;
mult_ip : in STD_LOGIC;
mult_logic : in STD_LOGIC;
clear : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0);
ind : out STD_LOGIC_VECTOR (3 downto 0)
);
end entity;
architecture rtl of calc is
-- IP-блок
component multiplier
port (
dataa : in STD_LOGIC_VECTOR (7 downto 0);
datab : in STD_LOGIC_VECTOR (7 downto 0);
result: out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
constant A : integer := 125;
constant B : integer := 3;
constant C : integer := 5;
constant D : integer := 11;
signal mult_result_ip : STD_LOGIC_VECTOR (15 downto 0);
signal mult_result_logic : integer := 0;
signal result_int : INTEGER range 0 to 65535 := 0;
signal ip_mult: STD_LOGIC_VECTOR (15 downto 0);
signal logic_mult : integer := 0;
signal counter: integer := 0;
signal clk_div: integer := 0;
begin
process(clk)
begin
if rising_edge(clk) then
ip_mult <= mult_result_ip;
logic_mult <= mult_result_logic;
end if;
end process;
-- Подключение IP-блока умножения (константы подаются на вход)
mult_inst: entity work.mult
port map (
dataa => std_logic_vector(to_unsigned(A, 8)),
datab => std_logic_vector(to_unsigned(B, 8)),
result => mult_result_ip
);
mult_result_logic <= C*D;
-- Захват результата по кнопке
process(clk)
begin
if rising_edge(clk) then
if clear = '0' then
result_int <= 0;
elsif mult_ip = '0' then
result_int <= to_integer(unsigned(mult_result_ip));
elsif mult_logic = '0' then
result_int <= mult_result_logic;
end if;
end if;
end process;
-- Вывод на индикатор (последняя цифра)
-- process(result_int)
-- variable digit : integer;
-- begin
-- digit := result_int mod 10;
-- ind <= "1110"; -- включаем правый индикатор
--
-- case digit is
-- when 0 => seg <= "1000000";
-- when 1 => seg <= "1111001";
-- when 2 => seg <= "0100100";
-- when 3 => seg <= "0110000";
-- when 4 => seg <= "0011001";
-- when 5 => seg <= "0010010";
-- when 6 => seg <= "0000010";
-- when 7 => seg <= "1111000";
-- when 8 => seg <= "0000000";
-- when 9 => seg <= "0010000";
-- when others => seg <= "1111111";
-- end case;
-- end process;
process(clk)
variable temp : integer;
variable d0, d1, d2, d3 : integer;
begin
if rising_edge(clk) then
-- Делитель частоты
if clk_div < 50000 then
clk_div <= clk_div + 1;
else
clk_div <= 0;
counter <= counter + 1;
if counter = 4 then
counter <= 0;
end if;
end if;
-- Разбиваем результат на 4 цифры
temp := result_int;
d0 := temp mod 10; temp := temp / 10;
d1 := temp mod 10; temp := temp / 10;
d2 := temp mod 10; temp := temp / 10;
d3 := temp mod 10;
-- Выбираем, какой индикатор включить и какую цифру показать
case counter is
when 0 =>
ind <= "1110"; -- правый (единицы)
case d0 is
when 0 => seg <= "1000000";
when 1 => seg <= "1111001";
when 2 => seg <= "0100100";
when 3 => seg <= "0110000";
when 4 => seg <= "0011001";
when 5 => seg <= "0010010";
when 6 => seg <= "0000010";
when 7 => seg <= "1111000";
when 8 => seg <= "0000000";
when 9 => seg <= "0010000";
when others => seg <= "1111111";
end case;
when 1 =>
ind <= "1101"; -- второй (десятки)
case d1 is
when 0 => seg <= "1000000";
when 1 => seg <= "1111001";
when 2 => seg <= "0100100";
when 3 => seg <= "0110000";
when 4 => seg <= "0011001";
when 5 => seg <= "0010010";
when 6 => seg <= "0000010";
when 7 => seg <= "1111000";
when 8 => seg <= "0000000";
when 9 => seg <= "0010000";
when others => seg <= "1111111";
end case;
when 2 =>
ind <= "1011"; -- третий (сотни)
case d2 is
when 0 => seg <= "1000000";
when 1 => seg <= "1111001";
when 2 => seg <= "0100100";
when 3 => seg <= "0110000";
when 4 => seg <= "0011001";
when 5 => seg <= "0010010";
when 6 => seg <= "0000010";
when 7 => seg <= "1111000";
when 8 => seg <= "0000000";
when 9 => seg <= "0010000";
when others => seg <= "1111111";
end case;
when 3 =>
ind <= "0111"; -- левый (тысячи)
case d3 is
when 0 => seg <= "1000000";
when 1 => seg <= "1111001";
when 2 => seg <= "0100100";
when 3 => seg <= "0110000";
when 4 => seg <= "0011001";
when 5 => seg <= "0010010";
when 6 => seg <= "0000010";
when 7 => seg <= "1111000";
when 8 => seg <= "0000000";
when 9 => seg <= "0010000";
when others => seg <= "1111111";
end case;
when others => null;
end case;
end if;
end process;
end rtl;
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.ALL;
--
--entity calc_mod is
-- Port (
-- clk : in STD_LOGIC;
-- key_ip : in STD_LOGIC;
-- key_logic : in STD_LOGIC;
-- clear : in STD_LOGIC;
-- seg : out STD_LOGIC_VECTOR (6 downto 0);
-- ind : out STD_LOGIC_VECTOR (3 downto 0);
-- op_A : out STD_LOGIC_VECTOR (7 downto 0);
-- op_B : out STD_LOGIC_VECTOR (7 downto 0);
-- op_C : out STD_LOGIC_VECTOR (7 downto 0);
-- op_D : out STD_LOGIC_VECTOR (7 downto 0);
-- debug_clk: out STD_LOGIC
-- );
--end calc_mod;
--
--architecture rtl of calc_mod is
--
-- constant C_SP_WIDTH : natural := 32;
-- signal s_sp_source : std_logic_vector(C_SP_WIDTH-1 downto 0) := (others => '0');
--
-- -- Операнды из Signal Probe
-- signal A_vec : std_logic_vector(7 downto 0);
-- signal B_vec : std_logic_vector(7 downto 0);
-- signal C_vec : std_logic_vector(7 downto 0);
-- signal D_vec : std_logic_vector(7 downto 0);
--
-- -- Преобразованные в integer
-- signal A_int : integer := 0;
-- signal B_int : integer := 0;
-- signal C_int : integer := 0;
-- signal D_int : integer := 0;
--
-- signal mult_ip_result : STD_LOGIC_VECTOR (15 downto 0);
-- signal mult_logic_result : integer := 0;
-- signal final_result : STD_LOGIC_VECTOR (15 downto 0);
--
-- signal clk_debug : std_logic := '0';
-- signal counter : integer := 0;
--
-- component multiplier_ip
-- port (
-- a : in integer;
-- b : in integer;
-- result : out STD_LOGIC_VECTOR (15 downto 0)
-- );
-- end component;
--
-- component multiplier_logic
-- port (
-- a : in integer;
-- b : in integer;
-- result : out integer
-- );
-- end component;
--
-- component mult_ctrl
-- port (
-- clk : in STD_LOGIC;
-- key_ip : in STD_LOGIC;
-- key_logic : in STD_LOGIC;
-- clear : in STD_LOGIC;
-- mult_ip_in : in STD_LOGIC_VECTOR (15 downto 0);
-- mult_logic_in : in integer;
-- result : out STD_LOGIC_VECTOR (15 downto 0)
-- );
-- end component;
--
-- component display_new
-- port (
-- --clk : in STD_LOGIC;
-- result_int : in integer;
-- seg : out STD_LOGIC_VECTOR (6 downto 0);
-- an : out STD_LOGIC_VECTOR (3 downto 0)
-- );
-- end component;
--
--begin
--
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if counter = 5000000 then
-- counter <= 0;
-- clk_debug <= not clk_debug;
-- else
-- counter <= counter + 1;
-- end if;
-- end if;
-- end process;
--
-- debug_clk <= clk_debug;
--
-- op_A <= A_vec;
-- op_B <= B_vec;
-- op_C <= A_vec;
-- op_D <= A_vec;
--
-- sprobe: entity work.signalprobe
-- generic map(SIM => 0, W => C_SP_WIDTH, ID => "NONE", IDX => -1)
-- port map(source => s_sp_source);
--
-- -- Разделение 32-битной шины на 4 байта
-- A_vec <= s_sp_source(7 downto 0);
-- B_vec <= s_sp_source(15 downto 8);
--
-- -- Преобразование std_logic_vector в integer
-- A_int <= to_integer(unsigned(A_vec));
-- B_int <= to_integer(unsigned(B_vec));
--
-- ip_mult_inst: entity work.mult_ip
-- port map (
-- a => A_int,
-- b => B_int,
-- result => mult_ip_result
-- );
--
-- logic_mult_inst: entity work.mult_logic
-- port map (
-- a => C_int,
-- b => D_int,
-- result => mult_logic_result
-- );
--
-- ctrl_inst: entity work.mult_ctrl
-- port map (
-- clk => clk,
-- key_ip => key_ip,
-- key_logic => key_logic,
-- clear => clear,
-- mult_ip_in => mult_ip_result,
-- mult_logic_in => mult_logic_result,
-- result => final_result
-- );
--
-- disp_inst: entity work.display_new
-- port map (
-- --clk => clk,
-- result_int => final_result,
-- seg => seg,
-- an => ind
-- );
--
--end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity calc_mod is
Port (
clk : in STD_LOGIC;
key_ip : in STD_LOGIC;
key_logic : in STD_LOGIC;
clear : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (6 downto 0);
ind : out STD_LOGIC_VECTOR (3 downto 0)
);
end calc_mod;
architecture Structural of calc_mod is
constant C_SP_WIDTH : natural := 16;
signal s_sp_source : std_logic_vector(C_SP_WIDTH-1 downto 0) := (others => '0');
signal A_vec : std_logic_vector(7 downto 0);
signal B_vec : std_logic_vector(7 downto 0);
--signal A_int : integer := 0;
--signal B_int : integer := 0;
signal slow_ip : std_logic := '0';
signal slow_logic : std_logic := '0';
signal slow_ip_delayed : std_logic := '0'; -- Задержанный для IP
signal slow_logic_delayed : std_logic := '0'; -- Задержанный для Logic
-- signal a_ip : integer := 0;
-- signal b_ip : integer := 0;
-- signal a_logic : integer := 0;
-- signal b_logic : integer := 0;
signal a_ip_reg : std_logic_vector(7 downto 0) := (others => '0');
signal b_ip_reg : std_logic_vector(7 downto 0) := (others => '0');
signal a_logic_reg : std_logic_vector(7 downto 0) := (others => '0');
signal b_logic_reg : std_logic_vector(7 downto 0) := (others => '0');
signal res_ip_vec: std_logic_vector(15 downto 0) := (others => '0');
signal res_logic_vec : std_logic_vector(15 downto 0) := (others => '0');
-- signal res_ip : integer := 0;
-- signal res_logic : integer := 0;
-- signal res_ip_reg : integer := 0;
-- signal res_logic_reg : integer := 0;
-- Первые регистры результатов (по slow)
signal res_ip_reg1 : std_logic_vector(15 downto 0) := (others => '0');
signal res_logic_reg1 : std_logic_vector(15 downto 0) := (others => '0');
-- Вторые регистры результатов (по задержанному slow)
signal res_ip_reg2 : std_logic_vector(15 downto 0) := (others => '0');
signal res_logic_reg2 : std_logic_vector(15 downto 0) := (others => '0');
signal display_value : std_logic_vector(15 downto 0) := (others => '0');
-- component slow_pulse
-- port ( clk, key, clear : in std_logic; pulse : out std_logic );
-- end component;
component slow_pulse
port ( clk, key, clear : in std_logic; mult_en, save_en : out std_logic );
end component;
component input_reg
port ( clk, slow, clear : in std_logic; value_in : in std_logic_vector(7 downto 0); value_out : out std_logic_vector(7 downto 0) );
end component;
component mult_ip
port ( a, b : in std_logic_vector(7 downto 0); result : out STD_LOGIC_VECTOR (15 downto 0) );
end component;
component mult_logic
port ( a, b : in std_logic_vector(7 downto 0); result : out std_logic_vector(15 downto 0) );
end component;
component res_reg
generic ( HOLD_VALUE : boolean := false );
port ( clk, slow, clear : in std_logic; value_in : in std_logic_vector(15 downto 0); value_out : out std_logic_vector(15 downto 0) );
end component;
component delay
generic ( DELAY_CYCLES : integer := 2 );
port ( clk, clear, sig : in std_logic; sig_delayed : out std_logic );
end component;
component display_mux
port ( clk, slow_ip, slow_logic, clear: in std_logic; res_ip, res_logic: in std_logic_vector(15 downto 0); value_out : out std_logic_vector(15 downto 0));
end component;
component display_new
port ( result : in std_logic_vector(15 downto 0); seg : out STD_LOGIC_VECTOR (6 downto 0); an : out STD_LOGIC_VECTOR (3 downto 0) );
end component;
-- Для IP
signal mult_en_ip : std_logic := '0';
signal save_en_ip : std_logic := '0';
-- Для Logic
signal mult_en_logic : std_logic := '0';
signal save_en_logic : std_logic := '0';
signal save_en_ip_delayed : std_logic := '0';
signal save_en_logic_delayed : std_logic := '0';
component alpll
port (
inclk0 : in std_logic;
c0 : out std_logic; -- ← новый такт (100 МГц)
locked : out std_logic
);
end component;
signal clk_pll : std_logic := '0';
signal pll_locked : std_logic := '0';
--signal HOLD_VALUE: boolean;
begin
sprobe: entity work.signalprobe
generic map(SIM => 0, W => C_SP_WIDTH, ID => "NONE", IDX => -1)
port map(source => s_sp_source);
U_PLL: alpll port map (
inclk0 => clk, -- ← вход 50 МГц
c0 => clk_pll, -- ← выход 100 МГц
locked => pll_locked
);
A_vec <= s_sp_source(7 downto 0);
B_vec <= s_sp_source(15 downto 8);
-- U_slow_ip: slow_pulse port map (clk => clk, key => key_ip, clear => clear, pulse => slow_ip);
-- U_slow_logic: slow_pulse port map (clk => clk, key => key_logic, clear => clear, pulse => slow_logic);
U_slow_ip: slow_pulse
port map (
clk => clk_pll,
key => key_ip,
clear => clear,
mult_en => mult_en_ip, -- ← 1-й выход (для захвата данных)
save_en => save_en_ip -- ← 2-й выход (для захвата результата)
);
U_slow_logic: slow_pulse
port map (
clk => clk_pll,
key => key_logic,
clear => clear,
mult_en => mult_en_logic, -- ← 1-й выход (для захвата данных)
save_en => save_en_logic -- ← 2-й выход (для захвата результата)
);
-- U_delay_ip: delay generic map (DELAY_CYCLES => 1) port map (clk => clk, clear => clear, sig => slow_ip, sig_delayed => slow_ip_delayed);
-- U_delay_logic: delay generic map (DELAY_CYCLES => 1) port map (clk => clk, clear => clear, sig => slow_logic, sig_delayed => slow_logic_delayed);
-- U_reg_A_ip: input_reg port map (clk => clk, slow => slow_ip, clear => clear, value_in => A_vec, value_out => a_ip_reg);
-- U_reg_B_ip: input_reg port map (clk => clk, slow => slow_ip, clear => clear, value_in => B_vec, value_out => b_ip_reg);
U_reg_A_ip: input_reg port map (clk => clk_pll, slow => mult_en_ip, clear => clear, value_in => A_vec, value_out => a_ip_reg);
U_reg_B_ip: input_reg port map (clk => clk_pll, slow => mult_en_ip, clear => clear, value_in => B_vec, value_out => b_ip_reg);
-- U_reg_A_logic: input_reg port map (clk => clk, slow => slow_logic, clear => clear,
-- value_in => A_vec, value_out => a_logic_reg);
-- U_reg_B_logic: input_reg port map (clk => clk, slow => slow_logic, clear => clear,
-- value_in => B_vec, value_out => b_logic_reg);
U_reg_A_logic: input_reg port map (clk => clk_pll, slow => mult_en_logic, clear => clear,
value_in => A_vec, value_out => a_logic_reg);
U_reg_B_logic: input_reg port map (clk => clk_pll, slow => mult_en_logic, clear => clear,
value_in => B_vec, value_out => b_logic_reg);
-- Умножители (оба получают A и B)
U_mult_ip: mult_ip port map (a => a_ip_reg, b => b_ip_reg, result => res_ip_vec);
U_mult_logic: mult_logic port map (a => a_logic_reg, b => b_logic_reg,
result => res_logic_vec);
-- U_res_ip1: res_reg port map (clk => clk, slow => slow_ip_delayed, clear => clear,
-- value_in => res_ip_vec, value_out => res_ip_reg1);
-- U_res_logic1: res_reg port map (clk => clk, slow => slow_logic_delayed, clear => clear,
-- value_in => res_logic_vec, value_out => res_logic_reg1);
U_res_ip1: res_reg generic map (HOLD_VALUE => false) port map (clk => clk_pll, slow => save_en_ip, clear => clear,
value_in => res_ip_vec, value_out => res_ip_reg1);
U_res_logic1: res_reg generic map (HOLD_VALUE => false) port map (clk => clk_pll, slow => save_en_logic, clear => clear,
value_in => res_logic_vec, value_out => res_logic_reg1);
U_delay_save_ip : delay generic map (DELAY_CYCLES => 1) port map (clk => clk_pll, clear => clear, sig => save_en_ip, sig_delayed => save_en_ip_delayed);
U_delay_save_logic : delay generic map (DELAY_CYCLES => 1) port map (clk => clk_pll, clear => clear, sig => save_en_logic, sig_delayed => save_en_logic_delayed);
-- Вторые регистры результатов (по задержанному slow)
U_res_ip2: res_reg generic map (HOLD_VALUE => true) port map (clk => clk_pll, slow => save_en_ip_delayed, clear => clear,
value_in => res_ip_reg1, value_out => res_ip_reg2);
U_res_logic2: res_reg generic map (HOLD_VALUE => true) port map (clk => clk_pll, slow => save_en_logic_delayed, clear => clear,
value_in => res_logic_reg1, value_out => res_logic_reg2);
U_mux: display_mux port map (
clk => clk,
slow_ip => save_en_ip_delayed,
slow_logic => save_en_logic_delayed,
clear => clear,
res_ip => res_ip_reg2,
res_logic => res_logic_reg2,
value_out => display_value
);
U_disp: display_new port map (result => display_value, seg => seg, an => ind);
end Structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mult_ctrl is
Port (
clk : in STD_LOGIC;
key_ip : in STD_LOGIC;
key_logic : in STD_LOGIC;
clear : in STD_LOGIC;
mult_ip_in : in STD_LOGIC_VECTOR (15 downto 0);
mult_logic_in : in integer;
result : out STD_LOGIC_VECTOR (15 downto 0)
);
end mult_ctrl;
architecture rtl of mult_ctrl is
signal start_ip: std_logic := '0';
signal start_logic: std_logic := '0';
signal result_reg: std_logic_vector(15 downto 0) := (others => '0');
begin
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if clear = '0' then
-- result <= (others => '0');
-- elsif key_ip = '0' then
-- result <= mult_ip_in;
-- elsif key_logic = '0' then
-- result <= std_logic_vector(to_unsigned(mult_logic_in,16));
-- end if;
-- end if;
-- end process;
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if clear = '0' then
-- start_ip <= '0';
-- start_logic <= '0';
-- result_reg <= (others => '0');
-- else
-- -- Ловим фронт нажатия key_ip
-- if key_ip = '0' and start_ip = '0' then
-- start_ip <= '1';
-- else
-- start_ip <= '0';
-- end if;
--
-- --result_reg <= (others => '0');
--
-- -- Защёлкиваем результат (через 1 такт после запуска)
-- if start_ip = '1' then
-- result_reg <= mult_ip_in;
---- else
---- result_reg <= (others => '0');
-- end if;
--
-- -- Ловим фронт нажатия key_logic
-- if key_logic = '0' and start_logic = '0' then
-- start_logic <= '1';
-- else
-- start_logic <= '0';
-- end if;
--
-- if start_logic = '1' then
-- result_reg <= std_logic_vector(to_unsigned(mult_logic_in, 16));
---- else
---- result_reg <= (others => '0');
-- end if;
-- end if;
-- end if;
-- end process;
process(clk)
begin
if rising_edge(clk) then
if clear = '0' then
start_ip <= '0';
start_logic <= '0';
result_reg <= (others => '0');
else
-- Ловим фронт нажатия key_ip (на один такт)
if key_ip = '0' and start_ip = '0' then
start_ip <= '1';
else
start_ip <= '0';
end if;
-- Ловим фронт нажатия key_logic
if key_logic = '0' and start_logic = '0' then
start_logic <= '1';
else
start_logic <= '0';
end if;
if start_ip = '1' then
result_reg <= mult_ip_in;
elsif start_logic = '1' then
result_reg <= std_logic_vector(to_unsigned(mult_logic_in, 16));
else
result_reg <= (others => '0');
end if;
-- Защёлкиваем результат (через 1 такт после запуска)
-- if start_ip = '1' then
-- result_reg <= mult_ip_in;
-- end if;
--
-- if start_logic = '1' then
-- result_reg <= std_logic_vector(to_unsigned(mult_logic_in, 16));
-- end if;
end if;
end if;
end process;
result <= result_reg;
end rtl;
--architecture rtl of mult_ctrl is
-- signal key_ip_prev : std_logic := '1';
-- signal key_logic_prev : std_logic := '1';
--begin
--
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if clear = '0' then
-- result <= (others => '0');
-- key_ip_prev <= '1';
-- key_logic_prev <= '1';
-- else
-- -- Запоминаем предыдущее состояние кнопок
-- key_ip_prev <= key_ip;
-- key_logic_prev <= key_logic;
--
-- -- По умолчанию результат 0
-- result <= (others => '0');
--
-- -- IP-умножение: ловим фронт (1 -> 0)
-- if key_ip_prev = '1' and key_ip = '0' then
-- result <= mult_ip_in;
-- end if;
--
-- -- Логическое умножение: ловим фронт (1 -> 0)
-- if key_logic_prev = '1' and key_logic = '0' then
-- result <= std_logic_vector(to_unsigned(mult_logic_in, 16));
-- end if;
-- end if;
-- end if;
-- end process;
--
--end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mult_logic is
Port (
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
result : out std_logic_vector(15 downto 0)
);
end mult_logic;
architecture rtl of mult_logic is
begin
result <= std_logic_vector(unsigned(a) * unsigned(b));
end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mult_ip is
Port (
a : in std_logic_vector(7 downto 0);
b : in std_logic_vector(7 downto 0);
result : out STD_LOGIC_VECTOR (15 downto 0)
);
end mult_ip;
architecture rtl of mult_ip is
component multiplier
port (
dataa : in STD_LOGIC_VECTOR (7 downto 0);
datab : in STD_LOGIC_VECTOR (7 downto 0);
result: out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
begin
mult_inst: entity work.mult
port map (
dataa => a,
datab => b,
result => result
);
end rtl;
-- megafunction wizard: %In-System Sources and Probes%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsource_probe
-- ============================================================
-- File Name: signalprobe.vhd
-- Megafunction Name(s):
-- altsource_probe
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
-- ************************************************************
--=============================
-- Developed by KST. Ver. 1.2.
--=============================
----------------------------------------------------------------------------------
-- Company: ������-�����
-- Engineer: ��������� ��������
--
-- Create Date: 15:50 12.05.2012
-- Design Name:
-- Module Name: signalprobe - structural
-- Project Name:
-- Target Devices:
-- Tool versions: Notepad++
-- Description: ������� ��� ����������� altsource_probe
-- (������ ���� source)
--
-- Dependencies: altsource_probe
--
-- Revision:
-- Revision 1.0 - ��� ����� probe, ������ source
-- Revision 1.1 - ��������� ����� �� ������������, ����������� ��������
-- �������������� Connectivity check.
-- �������� �������� SIM, ����������� �����������
-- ��� ���������
-- Revision 1.2 - �������� �������� IDX - ������ ������ signal probe
-- ���� �� �� ������ ��� ������ ������������� ��������,
-- �� ������ ����������� �������������
--
--
-- Additional Comments:
-- ����, ���������� � ������� MegaWizard, ��� ������� ������� �������������
-- ��� ���������� ����� �������������.
-- � ������ ����� �� ������������ ���� probe � �� �� ��������� �� ����� �
-- In-System Sources and Probes Editor.
-- ����� � ����� ������ ����� (����� �� ���������) ��������� ��������
-- �������������� Conectivity Check.
----------------------------------------------------------------------------------
-- <�����> : entity work.signalprobe
-- generic map(SIM => , W => , ID => "NONE") port map(source => );
----------------------------------------------------------------------------------
library ieee, work;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
LIBRARY altera_mf;
USE altera_mf.all;
entity signalprobe is
generic(SIM : integer range 0 to 1 := 0; --������� ���������
W : integer;--����������� ����� source
ID : string := "NONE";--����������� ������ signal probe
IDX : integer := -1 --������ ������ signal probe
);
port(source : out std_logic_vector (W-1 downto 0));
end signalprobe;
architecture structural of signalprobe is
component altsource_probe
generic (
enable_metastability : string := "NO";
instance_id : string := "UNUSED";
lpm_hint : string := "altsource_probe";
lpm_type : string := "altsource_probe";
probe_width : natural := 0;
sld_auto_instance_index : string := "YES";
sld_instance_index : natural := 0;
source_initial_value : string := "0";
source_width : natural := 1 );
port(
--probe : in std_logic_vector(probe_width-1 downto 0) := (others => '0');
source : out std_logic_vector(source_width-1 downto 0);
source_clk : in std_logic := '0';
source_ena : in std_logic := '1'
);
end component;
function index(idx : in integer) return natural is
begin
if (idx < 0) then
return(0);
else
return(idx);
end if;
end index;
function autoindex(idx : in integer) return string is
begin
if (idx < 0) then
return("YES");
else
return("NO");
end if;
end autoindex;
constant INST_IDX : natural := index(IDX);
constant AUTO_INST_IDX : string := autoindex(IDX);
begin
--���� �� ���������, �� ������������ �����������
a: if SIM = 0 generate
altsource_probe_component : altsource_probe
GENERIC MAP (
instance_id => ID,
sld_auto_instance_index => AUTO_INST_IDX,
sld_instance_index => INST_IDX,
source_initial_value => "0",
source_width => W)
--PORT MAP(probe => "0", source => source);
PORT MAP(source => source);
end generate;
--���� �� ���������, �� ����������� �� �����
b: if SIM > 0 generate
source <= (others => '0');
end generate;
end structural;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity display_new is
Port (
result : std_logic_vector(15 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0);
an : out STD_LOGIC_VECTOR (3 downto 0)
);
end display_new;
architecture rtl of display_new is
-- Отображаем только младшие 4 бита (одна HEX цифра)
signal hex_digit : integer range 0 to 15;
begin
hex_digit <= to_integer(unsigned(result(3 downto 0)));
-- Включаем только правый индикатор
an <= "1110";
-- Декодер одной HEX цифры (0-15)
process(hex_digit)
begin
case hex_digit is
when 0 => seg <= "1000000";
when 1 => seg <= "1111001";
when 2 => seg <= "0100100";
when 3 => seg <= "0110000";
when 4 => seg <= "0011001";
when 5 => seg <= "0010010";
when 6 => seg <= "0000010";
when 7 => seg <= "1111000";
when 8 => seg <= "0000000";
when 9 => seg <= "0010000";
when 10 => seg <= "0001000";
when 11 => seg <= "0000011";
when 12 => seg <= "1000110";
when 13 => seg <= "0100001";
when 14 => seg <= "0000110";
when 15 => seg <= "0001110";
when others => seg <= "1111111";
end case;
end process;
end rtl;
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--
--entity slow_pulse is
-- Port (
-- clk : in STD_LOGIC;
-- key : in STD_LOGIC;
-- clear : in STD_LOGIC;
-- pulse : out STD_LOGIC
-- );
--end slow_pulse;
--
--architecture rtl of slow_pulse is
-- signal key_prev : std_logic := '1';
--begin
-- process(clk)
-- begin
-- if rising_edge(clk) then
-- if clear = '0' then
-- key_prev <= '1';
-- pulse <= '0';
-- else
-- if key_prev = '1' and key = '0' then
-- pulse <= '1';
-- else
-- pulse <= '0';
-- end if;
-- key_prev <= key;
-- end if;
-- end if;
-- end process;
--end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity slow_pulse is
Port (
clk : in STD_LOGIC;
key : in STD_LOGIC;
clear : in STD_LOGIC;
mult_en : out STD_LOGIC; -- ← для захвата A и B (1-й такт)
save_en : out STD_LOGIC -- ← для захвата результата (2-й такт)
);
end slow_pulse;
architecture rtl of slow_pulse is
signal key_prev : std_logic := '1';
signal mult_en_s : std_logic := '0';
signal save_en_s : std_logic := '0';
signal counter : integer range 0 to 3 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if clear = '0' then
key_prev <= '1';
counter <= 0;
mult_en <= '0';
save_en <= '0';
else
key_prev <= key;
if key_prev = '1' and key = '0' then -- нажатие
counter <= 1;
mult_en <= '1';
save_en <= '0';
elsif counter = 1 then
counter <= 0;
mult_en <= '0';
save_en <= '1';
else
mult_en <= '0';
save_en <= '0';
end if;
end if;
end if;
end process;
-- begin
-- if rising_edge(clk) then
-- if clear = '0' then
-- key_prev <= '1';
-- mult_en_s <= '0';
-- save_en_s <= '0';
-- counter <= 0;
-- else
-- key_prev <= key;
--
-- if key_prev = '1' and key = '0' then
-- mult_en_s <= '1';
-- save_en_s <= '0';
-- counter <= 0;
-- elsif mult_en_s = '1' then
-- if counter < 3 then
-- counter <= counter + 1;
-- else
-- counter <= 0;
-- mult_en_s <= '0';
-- save_en_s <= '1';
-- end if;
-- elsif save_en_s = '1' then
-- save_en_s <= '0';
-- end if;
-- end if;
-- end if;
-- end process;
--
-- mult_en <= mult_en_s; -- ← выход
-- save_en <= save_en_s;
end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity res_reg is
Generic (
HOLD_VALUE : boolean := false -- ← true = хранить, false = 1 такт
);
Port (
clk : in STD_LOGIC;
slow : in STD_LOGIC;
clear : in STD_LOGIC;
value_in: in std_logic_vector(15 downto 0);
value_out: out std_logic_vector(15 downto 0) := (others => '0')
);
end res_reg;
architecture rtl of res_reg is
begin
process(clk,clear)
begin
if clear = '0' then
value_out <= (others => '0');
elsif rising_edge(clk) then
if HOLD_VALUE = false then
value_out <= value_in;
else
if slow = '1' then
value_out <= value_in;
end if;
end if;
end if;
end process;
end rtl;
ibrary IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity input_reg is
Port (
clk : in STD_LOGIC;
slow : in STD_LOGIC;
clear : in STD_LOGIC;
value_in: in std_logic_vector(7 downto 0);
value_out: out std_logic_vector(7 downto 0) := (others => '0')
);
end input_reg;
architecture rtl of input_reg is
begin
process(clk)
begin
if rising_edge(clk) then
if clear = '0' then
value_out <= (others => '0');
elsif slow = '1' then
value_out <= value_in;
else
value_out <= (others => '0'); -- ✅ Только 1 такт!
end if;
end if;
end process;
end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity display_mux is
Port (
clk : in STD_LOGIC;
slow_ip : in STD_LOGIC;
slow_logic : in STD_LOGIC;
clear : in STD_LOGIC;
res_ip : in std_logic_vector(15 downto 0);
res_logic : in std_logic_vector(15 downto 0);
value_out : out std_logic_vector(15 downto 0) := (others => '0')
);
end display_mux;
architecture rtl of display_mux is
signal saved_value : std_logic_vector(15 downto 0) := (others => '0');
begin
process(clk)
--process(slow_ip, slow_logic, res_ip, res_logic)
begin
if rising_edge(clk) then
if slow_ip = '1' then
saved_value <= res_ip;
elsif slow_logic = '1' then
saved_value <= res_logic;
elsif clear = '0' then
saved_value <= (others => '0');
end if;
end if;
end process;
value_out <= saved_value;
end rtl;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity delay is
Generic ( DELAY_CYCLES : integer := 2 ); -- сколько тактов задержки
Port (
clk : in STD_LOGIC;
clear : in STD_LOGIC;
sig : in STD_LOGIC;
sig_delayed : out STD_LOGIC
);
end delay;
architecture rtl of delay is
signal delay_chain : std_logic_vector(DELAY_CYCLES-1 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
if clear = '0' then
delay_chain <= (others => '0');
else
delay_chain <= delay_chain(DELAY_CYCLES-2 downto 0) & sig;
end if;
end if;
end process;
sig_delayed <= delay_chain(DELAY_CYCLES-1);
end rtl;