---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mult_controller is
    port (
        clk         : in  std_logic;
        show_btn    : in  std_logic;
        reset_btn   : in  std_logic;
        result_valid: out std_logic;
        bcd_0       : out integer range 0 to 9;
        bcd_1       : out integer range 0 to 9;
        bcd_2       : out integer range 0 to 9;
        bcd_3       : out integer range 0 to 9;
        bcd_4       : out integer range 0 to 9
    );
end mult_controller;

architecture rtl of mult_controller is

    constant NUM_A : unsigned(7 downto 0) := to_unsigned(12, 8);
    constant NUM_B : unsigned(7 downto 0) := to_unsigned(15, 8);

    -- ✅ ИЗМЕНЕНИЕ 1: Тип сигнала теперь std_logic_vector, как у IP-ядра
    signal mult_result : std_logic_vector(15 downto 0) := (others => '0');

    signal result_reg  : unsigned(15 downto 0) := (others => '0');
    signal enable_reg  : std_logic := '0';

    signal bcd_reg_0   : integer range 0 to 9 := 0;
    signal bcd_reg_1   : integer range 0 to 9 := 0;
    signal bcd_reg_2   : integer range 0 to 9 := 0;
    signal bcd_reg_3   : integer range 0 to 9 := 0;
    signal bcd_reg_4   : integer range 0 to 9 := 0;

begin

    -- ✅ ИЗМЕНЕНИЕ 2: Подключение БЕЗ преобразования типа
    u_mult_ip : entity work.mult_ip
        port map (
            dataa  => std_logic_vector(NUM_A),
            datab  => std_logic_vector(NUM_B),
            result => mult_result  -- Прямое подключение
        );

    -- Регистр результата
    process(clk)
    begin
        if rising_edge(clk) then
            if reset_btn = '1' then
                result_reg <= (others => '0');
                enable_reg <= '0';
            elsif show_btn = '1' then
                result_reg <= unsigned(mult_result); -- Преобразование при чтении
                enable_reg <= '1';
            end if;
        end if;
    end process;

    -- Преобразование в BCD
    process(clk)
    begin
        if rising_edge(clk) then
            if reset_btn = '1' then
                bcd_reg_0 <= 0; bcd_reg_1 <= 0; bcd_reg_2 <= 0;
                bcd_reg_3 <= 0; bcd_reg_4 <= 0;
            elsif show_btn = '1' then
                -- ✅ ИЗМЕНЕНИЕ 3: Явное приведение к unsigned для арифметики
                bcd_reg_0 <= to_integer((unsigned(mult_result) / 10000) mod 10);
                bcd_reg_1 <= to_integer((unsigned(mult_result) / 1000) mod 10);
                bcd_reg_2 <= to_integer((unsigned(mult_result) / 100) mod 10);
                bcd_reg_3 <= to_integer((unsigned(mult_result) / 10) mod 10);
                bcd_reg_4 <= to_integer(unsigned(mult_result) mod 10);
            end if;
        end if;
    end process;

    result_valid <= enable_reg;
    bcd_0 <= bcd_reg_0;
    bcd_1 <= bcd_reg_1;
    bcd_2 <= bcd_reg_2;
    bcd_3 <= bcd_reg_3;
    bcd_4 <= bcd_reg_4;

end rtl;