---

    -- Сигналы для синхронизации
    signal disp_en_sync1 : std_logic;
    signal disp_en_sync2 : std_logic;
    signal result_sync1 : std_logic_vector(15 downto 0);
    signal result_sync2 : std_logic_vector(15 downto 0);
    signal result_latched : std_logic_vector(15 downto 0);
    
begin

    ... (весь код до U_DISP_REG)

    -- =====================================================
    -- СИНХРОНИЗАЦИЯ: clk_fast → clk (50 МГц)
    -- =====================================================
    
    -- Защёлкиваем результат в быстром домене
    process(clk_fast)
    begin
        if rising_edge(clk_fast) then
            if disp_en = '1' then
                result_latched <= result_reg_out;
            end if;
        end if;
    end process;
    
    -- Двойная синхронизация в медленном домене
    process(clk)
    begin
        if rising_edge(clk) then
            disp_en_sync1 <= disp_en;
            disp_en_sync2 <= disp_en_sync1;
            result_sync1 <= result_latched;
            result_sync2 <= result_sync1;
        end if;
    end process;

    U_DISP_REG: entity work.display_register
        port map (
            clk      => clk,
            load     => disp_en_sync2,
            data_in  => result_sync2,
            data_out => disp_reg_out
        );