---

module MUX (IN, S, OUT);

input [2:0] S;
input [7:0] IN;
output OUT;

assign OUT = (S == 0) ? IN[0] :
(S == 1) ? IN[1] :
(S == 2) ? IN[2] :
(S == 3) ? IN[3] :
(S == 4) ? IN[4] :
(S == 5) ? IN[5] :
(S == 6) ? IN[6] : IN[7];

endmodule


`timescale 1ns/1ps

module MUX_TB;

reg [7:0] VAR1;
reg VAR2;
wire [7:0] In;
reg [2:0] Sel;
wire Out;

MUX DUT (.IN(In),
.S(Sel),
.OUT(Out));

assign In = VAR1 & {8{VAR2}};

initial begin
VAR2 = 0;
forever
begin
#10 Var2 = 1;
#10 VAR2 = 0;
#10;
end
end

initial
begin
Sel = 0;
forever
#30 Sel = Sel + 1;
end

initial
begin
VAR1 = 1;
forever
#30 VAR1 = VAR1<< 1;

initial begin
#240 $finish;
end

endmodule