---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity logic is
port (
    a      : in std_logic_vector(7 downto 0);
    b      : in std_logic_vector(7 downto 0);
    result : out std_logic_vector(15 downto 0)
);
end logic;

architecture rtl of logic is
    signal a_int : integer;
    signal b_int : integer;
    signal res_int : integer;
begin
    a_int <= to_integer(unsigned(a));
    b_int <= to_integer(unsigned(b));
    res_int <= a_int * b_int;
    result <= std_logic_vector(to_unsigned(res_int, 16));
end rtl;