---

/* STANDALONE DPHY CSR */
#define IMX95_CSR_PHY_MODE_CTRL			0x00
#define IMX95_CSR_PHY_FREQ_CTRL			0x04
#define IMX95_CSR_PHY_TEST_MODE_CTRL		0x08
#define IMX95_CSR_PHY_TEST_MODE_STS		0x0C

static const struct dw_dphy_reg imx95_dphy_regs[] = {
	[DPHY_RX_CFGCLKFREQRANGE] = PHY_REG(IMX95_CSR_PHY_FREQ_CTRL, 6, 0),
	[DPHY_RX_HSFREQRANGE] = PHY_REG(IMX95_CSR_PHY_FREQ_CTRL, 7, 16),
	[DPHY_RX_DATA_LANE_EN] = PHY_REG(IMX95_CSR_PHY_MODE_CTRL, 4, 4),
	[DPHY_RX_DATA_LANE_BASEDIR] = PHY_REG(IMX95_CSR_PHY_TEST_MODE_CTRL, 1, 0),
	[DPHY_RX_DATA_LANE_FORCETXSTOPMODE] = PHY_REG(IMX95_CSR_PHY_TEST_MODE_CTRL, 1, 4),
	[DPHY_RX_DATA_LANE_FORCERXMODE] = PHY_REG(IMX95_CSR_PHY_TEST_MODE_CTRL, 4, 8),
	[DPHY_RX_ENABLE_CLK_EXT] = PHY_REG(IMX95_CSR_PHY_TEST_MODE_CTRL, 1, 12),
	[DPHY_RX_PHY_ENABLE_BYP] = PHY_REG(IMX95_CSR_PHY_TEST_MODE_CTRL, 1, 14),
};

static void imx95_dphy_config(struct dw_dphy *priv)
{
	struct phy_configure_opts_mipi_dphy *config = &priv->config;
	u32 active_lanes = GENMASK(config->lanes - 1, 0);

printk("%s(%d) cfgclkfreqrange=%u\n",__FUNCTION__,__LINE__,priv->cfgclkfreqrange);
printk("%s(%d) hsfreqrange=%u\n",__FUNCTION__,__LINE__,priv->hsfreqrange);
	/* Configure the PHY frequency range */
	dphy_write(priv, DPHY_RX_CFGCLKFREQRANGE, priv->cfgclkfreqrange);
	dphy_write(priv, DPHY_RX_HSFREQRANGE, priv->hsfreqrange);

	dphy_write(priv, DPHY_RX_DATA_LANE_BASEDIR, 1);
	ndelay(15);

	dphy_write(priv, DPHY_RX_DATA_LANE_FORCERXMODE, active_lanes);
	ndelay(15);

	dphy_write(priv, DPHY_RX_DATA_LANE_EN, active_lanes);
	dphy_write(priv, DPHY_RX_DATA_LANE_FORCERXMODE, 0);
	dphy_write(priv, DPHY_RX_ENABLE_CLK_EXT, 1);
	dphy_write(priv, DPHY_RX_PHY_ENABLE_BYP, 1);
}

static const struct dw_dphy_config_ops imx95_dphy_cfg_ops = {
	.config = imx95_dphy_config,
};

static const struct dw_dphy_drv_data imx95_dphy_drvdata = {
	.regs = imx95_dphy_regs,
	.regs_size = ARRAY_SIZE(imx95_dphy_regs),
	.cfg_ops = &imx95_dphy_cfg_ops,
	.max_lanes = 4,
	.max_data_rate = 2500,
};

в логе постоянно:
root@imx95-19x19-lpddr5-evk:~# dmesg | grep cfgclkfreqrange
[ 2571.026793] imx95_dphy_config(512) cfgclkfreqrange=28
[ 3222.510226] imx95_dphy_config(512) cfgclkfreqrange=28
[ 3401.440671] imx95_dphy_config(512) cfgclkfreqrange=28
[ 3706.174335] imx95_dphy_config(512) cfgclkfreqrange=28
[ 3926.560878] imx95_dphy_config(512) cfgclkfreqrange=28
root@imx95-19x19-lpddr5-evk:~# dmesg | grep hsfreqrange
[ 2571.026797] imx95_dphy_config(513) hsfreqrange=44
[ 3222.510231] imx95_dphy_config(513) hsfreqrange=44
[ 3401.440676] imx95_dphy_config(513) hsfreqrange=44
[ 3706.174340] imx95_dphy_config(513) hsfreqrange=44
[ 3926.560882] imx95_dphy_config(513) hsfreqrange=44