---

(gdb) hbreak z_arm_reset
Hardware assisted breakpoint 4 at 0x8001a5c8: file /home/vovan/ZEPHYR_RTOS/zephyrproject/zephyr/arch/arm/core/cortex_m/reset.S, line 121.
(gdb) monitor reset halt
Resetting target with halt
Successfully halted device on reset
(gdb) c
Continuing.

Breakpoint 4, z_arm_reset () at /home/vovan/ZEPHYR_RTOS/zephyrproject/zephyr/arch/arm/core/cortex_m/reset.S:121
121         ldr r0, =z_main_stack + CONFIG_MAIN_STACK_SIZE
(gdb) stepi
122         msr msp, r0
(gdb) 
137         bl soc_reset_hook
(gdb) 
soc_reset_hook () at /home/vovan/ZEPHYR_RTOS/zephyrproject/zephyr/soc/nxp/imxrt/imxrt10xx/soc.c:364
364             SystemInit();
(gdb) 
0x800145ee      364             SystemInit();
(gdb) 
SystemInit () at /home/vovan/ZEPHYR_RTOS/zephyrproject/modules/hal/nxp/mcux/mcux-sdk-ng/devices/RT/RT1020/MIMXRT1024/system_MIMXRT1024.c:72
72        SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
(gdb) 
0x80047106      86          IOMUXC -> SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);
(gdb) 
0x80047108      86          IOMUXC -> SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);
(gdb) 
0x8004710a      70      void SystemInit (void) {
(gdb) 
0x8004710c      72        SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
(gdb) 
0x80047110      70      void SystemInit (void) {
(gdb) 
0x80047114      72        SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
(gdb) 
0x80047118      72        SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
(gdb) 
86          IOMUXC -> SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);
(gdb) 
89          if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
(gdb) 
0x80047122      89          if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
(gdb) 
0x80047124      89          if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
(gdb) 
101         while (i--)
(gdb) 
0x80047146      101         while (i--)
(gdb) 
0x80047148      101         while (i--)
(gdb) 
103           *dstAddr++ = *srcAddr++;
(gdb) 
0x8004714e      103           *dstAddr++ = *srcAddr++;
(gdb) 
101         while (i--)
(gdb) 
0x80047154      101         while (i--)
(gdb) 
0x80047156      101         while (i--)
(gdb) 
103           *dstAddr++ = *srcAddr++;
(gdb) 
0x8004714e      103           *dstAddr++ = *srcAddr++;
(gdb) 
101         while (i--)
(gdb) 
0x80047154      101         while (i--)
(gdb) 
0x80047156      101         while (i--)
(gdb) 
103           *dstAddr++ = *srcAddr++;
(gdb) 
0x8004714e      103           *dstAddr++ = *srcAddr++;
(gdb) 
101         while (i--)
(gdb) 
0x80047154      101         while (i--)
(gdb) 
0x80047156      101         while (i--)
(gdb) 
103           *dstAddr++ = *srcAddr++;
(gdb) 
0x8004714e      103           *dstAddr++ = *srcAddr++;
(gdb) 
101         while (i--)
(gdb) 
0x80047154      101         while (i--)
(gdb) 
0x80047156      101         while (i--)
(gdb) c
Continuing.

Program received signal SIGSEGV, Segmentation fault.
z_arm_usage_fault () at /home/vovan/ZEPHYR_RTOS/zephyrproject/zephyr/arch/arm/core/cortex_m/fault_s.S:80
80              mrs r0, MSP