---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sem_mult_top is
    port (
        clk            : in  std_logic;
        reset_btn      : in  std_logic;
        show_ip_btn    : in  std_logic;
        show_logic_btn : in  std_logic;
        ind            : out std_logic_vector(4 downto 0);
        seg            : out std_logic_vector(7 downto 0)
    );
end sem_mult_top;

architecture rtl of sem_mult_top is

    -- ✅ Объявляем тип массива для BCD цифр
    type bcd_array is array (0 to 4) of integer range 0 to 9;

    signal slow_ip, slow_ip_fall   : std_logic;
    signal slow_log, slow_log_fall : std_logic;
    
    signal ip_valid, log_valid     : std_logic;
    
    -- ✅ Используем объявленный тип
    signal ip_bcd      : bcd_array;
    signal log_bcd     : bcd_array;
    signal final_bcd   : bcd_array;
    signal final_valid : std_logic;
    
    signal char_0, char_1, char_2, char_3, char_4 : std_logic_vector(7 downto 0);

begin

    -- Генераторы slow
    u_slow_ip : entity work.slow_generator
        port map (clk => clk, reset_btn => reset_btn, show_btn => show_ip_btn,
                  slow => slow_ip, slow_fall => slow_ip_fall);
                  
    u_slow_log : entity work.slow_generator
        port map (clk => clk, reset_btn => reset_btn, show_btn => show_logic_btn,
                  slow => slow_log, slow_fall => slow_log_fall);

    -- Модули умножения
    u_ip_mult : entity work.ip_multiplier
        port map (clk => clk, slow => slow_ip, slow_fall => slow_ip_fall,
                  result_valid => ip_valid, 
                  bcd_0 => ip_bcd(0), bcd_1 => ip_bcd(1),
                  bcd_2 => ip_bcd(2), bcd_3 => ip_bcd(3), bcd_4 => ip_bcd(4));

    u_log_mult : entity work.logic_multiplier
        port map (clk => clk, slow => slow_log, slow_fall => slow_log_fall,
                  result_valid => log_valid,
                  bcd_0 => log_bcd(0), bcd_1 => log_bcd(1),
                  bcd_2 => log_bcd(2), bcd_3 => log_bcd(3), bcd_4 => log_bcd(4));

    -- Выбор активного результата
    final_valid <= ip_valid or log_valid;
    
    process(ip_valid, log_valid, ip_bcd, log_bcd)
    begin
        if ip_valid = '1' then
            final_bcd <= ip_bcd;
        else
            final_bcd <= log_bcd;
        end if;
    end process;

    -- BCD -> Сегменты
    u_bcd : entity work.bcd_converter
        port map (result_valid => final_valid, 
                  bcd_0 => final_bcd(0), bcd_1 => final_bcd(1),
                  bcd_2 => final_bcd(2), bcd_3 => final_bcd(3), bcd_4 => final_bcd(4),
                  char_0 => char_0, char_1 => char_1, char_2 => char_2, 
                  char_3 => char_3, char_4 => char_4);

    -- Дисплей
    u_disp : entity work.display_output
        port map (clk => clk, 
                  char_0 => char_0, char_1 => char_1, char_2 => char_2,
                  char_3 => char_3, char_4 => char_4, 
                  ind => ind, seg => seg);

end rtl;