---

module UserLogic(
    input clk_i,
    input nrst_i,
    input data_i,
    output reg trig_o);
    
    localparam S_IDLE = 3'b000,
               S_0  = 3'b001,
               S_01 = 3'b010,
               S_011 = 3'b011,
               S_0110= 3'b100,
               S_01101 = 3'b101,
               S_011010 = 3'b110;
               
    reg [2:0] state, next_state;
    
    // Регистр состояния
    always @(posedge clk_i or negedge nrst_i) begin
        if (!nrst_i)
            state <= S_IDLE;
        else
            state <= next_state;
    end
    
    // Логика выходов
     always @(posedge clk_i or negedge nrst_i) begin
        if (!nrst_i)begin
            trig_o <= 1'b0;
        end else begin
            if (next_state == S_011010)
                trig_o = 1'b1;
            else
                trig_o = 1'b0;
        end
    end
    
    // Логика переходов
    always @(*) begin
        case(state)
            S_IDLE: next_state = data_i ? S_IDLE : S_0;
            S_0: next_state = data_i ? S_01  : S_0;
            S_01:  next_state = data_i ? S_011 : S_0;
            S_011: next_state = data_i ? S_IDLE : S_0110;
            S_0110: next_state = data_i ? S_01101 : S_0110;
            S_01101: next_state = data_i ? S_011 : S_011010;
            S_011010: next_state = data_i ? S_01 : S_0;
            default: next_state = S_IDLE;
        endcase
    end
endmodule