---

library ieee;
use ieee.std_logic_1164.all;

entity display_register is
port (
    clk      : in std_logic;
    load     : in std_logic;
    data_in  : in std_logic_vector(15 downto 0);
    data_out : out std_logic_vector(15 downto 0)
);
end display_register;

architecture rtl of display_register is
    signal reg_data : std_logic_vector(15 downto 0) := (others => '0');
begin
    process(clk)
    begin
        if rising_edge(clk) then
            if load = '1' then
                reg_data <= data_in;
            end if;
        end if;
    end process;
    data_out <= reg_data;
end rtl;