---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bcd_converter is
    port (
        result_valid_ip   : in  std_logic;  -- ✅ Новый вход
        result_valid_log  : in  std_logic;  -- ✅ Новый вход
        ip_bcd_0          : in  integer range 0 to 9;
        ip_bcd_1          : in  integer range 0 to 9;
        ip_bcd_2          : in  integer range 0 to 9;
        ip_bcd_3          : in  integer range 0 to 9;
        ip_bcd_4          : in  integer range 0 to 9;
        log_bcd_0         : in  integer range 0 to 9;
        log_bcd_1         : in  integer range 0 to 9;
        log_bcd_2         : in  integer range 0 to 9;
        log_bcd_3         : in  integer range 0 to 9;
        log_bcd_4         : in  integer range 0 to 9;
        char_0            : out std_logic_vector(7 downto 0);
        char_1            : out std_logic_vector(7 downto 0);
        char_2            : out std_logic_vector(7 downto 0);
        char_3            : out std_logic_vector(7 downto 0);
        char_4            : out std_logic_vector(7 downto 0)
    );
end bcd_converter;

architecture rtl of bcd_converter is

    type hex_array is array (0 to 9) of std_logic_vector(7 downto 0);
    
    constant hex_codes : hex_array := (
        "10000001",  -- 0
        "11110011",  -- 1
        "01001001",  -- 2
        "01100001",  -- 3
        "00110011",  -- 4
        "00100101",  -- 5
        "00000101",  -- 6
        "11110001",  -- 7
        "00000001",  -- 8
        "00100001"   -- 9
    );

    -- ✅ Выбор активных BCD цифр
    signal selected_bcd_0 : integer range 0 to 9;
    signal selected_bcd_1 : integer range 0 to 9;
    signal selected_bcd_2 : integer range 0 to 9;
    signal selected_bcd_3 : integer range 0 to 9;
    signal selected_bcd_4 : integer range 0 to 9;
    signal result_valid   : std_logic;

begin

    -- ✅ Выбор результата внутри bcd_converter
    process(result_valid_ip, result_valid_log, 
            ip_bcd_0, ip_bcd_1, ip_bcd_2, ip_bcd_3, ip_bcd_4,
            log_bcd_0, log_bcd_1, log_bcd_2, log_bcd_3, log_bcd_4)
    begin
        if result_valid_ip = '1' then
            -- Активен IP умножитель
            selected_bcd_0 <= ip_bcd_0;
            selected_bcd_1 <= ip_bcd_1;
            selected_bcd_2 <= ip_bcd_2;
            selected_bcd_3 <= ip_bcd_3;
            selected_bcd_4 <= ip_bcd_4;
            result_valid <= '1';
        elsif result_valid_log = '1' then
            -- Активен логический умножитель
            selected_bcd_0 <= log_bcd_0;
            selected_bcd_1 <= log_bcd_1;
            selected_bcd_2 <= log_bcd_2;
            selected_bcd_3 <= log_bcd_3;
            selected_bcd_4 <= log_bcd_4;
            result_valid <= '1';
        else
            -- Ничего не активно
            selected_bcd_0 <= 0;
            selected_bcd_1 <= 0;
            selected_bcd_2 <= 0;
            selected_bcd_3 <= 0;
            selected_bcd_4 <= 0;
            result_valid <= '0';
        end if;
    end process;

    -- Преобразование в коды сегментов
    process(result_valid, selected_bcd_0, selected_bcd_1, selected_bcd_2, 
            selected_bcd_3, selected_bcd_4)
    begin
        if result_valid = '0' then
            char_0 <= "11111111";
            char_1 <= "11111111";
            char_2 <= "11111111";
            char_3 <= "11111111";
            char_4 <= "11111111";
        else
            char_0 <= hex_codes(selected_bcd_0);
            char_1 <= hex_codes(selected_bcd_1);
            char_2 <= hex_codes(selected_bcd_2);
            char_3 <= hex_codes(selected_bcd_3);
            char_4 <= hex_codes(selected_bcd_4);
        end if;
    end process;

end rtl;


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sem_mult_top is
    port (
        clk            : in  std_logic;
        reset_btn      : in  std_logic;
        show_ip_btn    : in  std_logic;
        show_logic_btn : in  std_logic;
        ind            : out std_logic_vector(4 downto 0);
        seg            : out std_logic_vector(7 downto 0)
    );
end sem_mult_top;

architecture rtl of sem_mult_top is

    signal slow_ip, slow_ip_fall   : std_logic;
    signal slow_log, slow_log_fall : std_logic;
    
    signal ip_valid, log_valid     : std_logic;
    
    -- ✅ BCD цифры от обоих умножителей
    signal ip_bcd_0, ip_bcd_1, ip_bcd_2, ip_bcd_3, ip_bcd_4     : integer range 0 to 9;
    signal log_bcd_0, log_bcd_1, log_bcd_2, log_bcd_3, log_bcd_4 : integer range 0 to 9;
    
    signal char_0, char_1, char_2, char_3, char_4 : std_logic_vector(7 downto 0);

begin

    -- Генераторы slow
    u_slow_ip : entity work.slow_generator
        port map (clk => clk, reset_btn => reset_btn, show_btn => show_ip_btn,
                  slow => slow_ip, slow_fall => slow_ip_fall);
                  
    u_slow_log : entity work.slow_generator
        port map (clk => clk, reset_btn => reset_btn, show_btn => show_logic_btn,
                  slow => slow_log, slow_fall => slow_log_fall);

    -- Модули умножения
    u_ip_mult : entity work.ip_multiplier
        port map (clk => clk, slow => slow_ip, slow_fall => slow_ip_fall,
                  result_valid => ip_valid, 
                  bcd_0 => ip_bcd_0, bcd_1 => ip_bcd_1,
                  bcd_2 => ip_bcd_2, bcd_3 => ip_bcd_3, bcd_4 => ip_bcd_4);

    u_log_mult : entity work.logic_multiplier
        port map (clk => clk, slow => slow_log, slow_fall => slow_log_fall,
                  result_valid => log_valid,
                  bcd_0 => log_bcd_0, bcd_1 => log_bcd_1,
                  bcd_2 => log_bcd_2, bcd_3 => log_bcd_3, bcd_4 => log_bcd_4);

    -- ✅ BCD конвертер с выбором результата ВНУТРИ
    u_bcd : entity work.bcd_converter
        port map (
            result_valid_ip  => ip_valid,
            result_valid_log => log_valid,
            ip_bcd_0         => ip_bcd_0, ip_bcd_1 => ip_bcd_1,
            ip_bcd_2         => ip_bcd_2, ip_bcd_3 => ip_bcd_3, ip_bcd_4 => ip_bcd_4,
            log_bcd_0        => log_bcd_0, log_bcd_1 => log_bcd_1,
            log_bcd_2        => log_bcd_2, log_bcd_3 => log_bcd_3, log_bcd_4 => log_bcd_4,
            char_0           => char_0, char_1 => char_1, char_2 => char_2,
            char_3           => char_3, char_4 => char_4
        );

    -- Дисплей
    u_disp : entity work.display_output
        port map (clk => clk, 
                  char_0 => char_0, char_1 => char_1, char_2 => char_2,
                  char_3 => char_3, char_4 => char_4, 
                  ind => ind, seg => seg);

end rtl;