---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_mult_top is
    port (
        clk             : in  std_logic;
        reset           : in  std_logic;
        result_valid    : out std_logic;
        mult_result     : out std_logic_vector(15 downto 0);
        slow            : out std_logic;
        counter_dbg     : out std_logic_vector(3 downto 0);
        reg_a_dbg       : out std_logic_vector(7 downto 0);
        reg_b_dbg       : out std_logic_vector(7 downto 0);
        display_reg_dbg : out std_logic_vector(15 downto 0)
    );
end test_mult_top;

architecture rtl of test_mult_top is

    signal slow_sig     : std_logic;
    signal counter_sig  : std_logic_vector(3 downto 0);

begin

    -- Генератор slow (автоматически каждые 10 тактов)
    u_slow_gen : entity work.slow_generator
        port map (
            clk     => clk,
            reset   => reset,
            slow    => slow_sig,
            counter => counter_sig
        );

    -- Контроллер умножения
    u_mult_ctrl : entity work.mult_test_controller
        port map (
            clk             => clk,
            reset           => reset,
            slow            => slow_sig,
            result_valid    => result_valid,
            mult_result     => mult_result,
            reg_a_dbg       => reg_a_dbg,
            reg_b_dbg       => reg_b_dbg,
            display_reg_dbg => display_reg_dbg
        );

    -- Выходы для SignalTap
    slow        <= slow_sig;
    counter_dbg <= counter_sig;

end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mult_test_controller is
    port (
        clk             : in  std_logic;
        reset           : in  std_logic;
        slow            : in  std_logic;
        result_valid    : out std_logic;
        mult_result     : out std_logic_vector(15 downto 0);
        reg_a_dbg       : out std_logic_vector(7 downto 0);
        reg_b_dbg       : out std_logic_vector(7 downto 0);
        display_reg_dbg : out std_logic_vector(15 downto 0)
    );
end mult_test_controller;

architecture rtl of mult_test_controller is

    constant NUM_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(12, 8));  -- 0x0C
    constant NUM_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(15, 8));  -- 0x0F

    -- Сигналы после мультиплексоров
    signal mux_a_out : std_logic_vector(7 downto 0);
    signal mux_b_out : std_logic_vector(7 downto 0);

    -- Регистры на входах умножителя
    signal reg_a : std_logic_vector(7 downto 0);
    signal reg_b : std_logic_vector(7 downto 0);

    -- Выход IP-умножителя
    signal mult_ip_result : std_logic_vector(15 downto 0);

    -- Регистр задержки slow
    signal slow_d1 : std_logic;
    
    -- Основной регистр результата (обнуляется)
    signal reg_c : std_logic_vector(15 downto 0);
    signal res_valid_reg : std_logic;

    -- Регистр БЕЗ СБРОСА для отладки
    signal display_reg : std_logic_vector(15 downto 0);

begin

    -- 1. Мультиплексоры (комбинационные)
    mux_a_out <= NUM_A when slow = '1' else (others => '0');
    mux_b_out <= NUM_B when slow = '1' else (others => '0');

    -- 2. Регистры после мультиплексоров (входы умножителя)
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_a <= (others => '0');
                reg_b <= (others => '0');
            else
                reg_a <= mux_a_out;
                reg_b <= mux_b_out;
            end if;
        end if;
    end process;

    -- 3. IP-ядро умножителя
    u_mult_ip : entity work.mult_ip
        port map (
            dataa  => reg_a,
            datab  => reg_b,
            result => mult_ip_result
        );

    -- 4. Задержка slow на 1 такт
    process(clk)
    begin
        if rising_edge(clk) then
            slow_d1 <= slow;
        end if;
    end process;

    -- 5. Основной выходной регистр (обнуляется по Варианту B)
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_c <= (others => '0');
                res_valid_reg <= '0';
            elsif slow_d1 = '1' then
                reg_c <= mult_ip_result;
                res_valid_reg <= '1';
            else
                reg_c <= (others => '0');
                res_valid_reg <= '0';
            end if;
        end if;
    end process;

    -- 6. Регистр БЕЗ СБРОСА для отладки
    process(clk)
    begin
        if rising_edge(clk) then
            if slow_d1 = '1' then
                display_reg <= mult_ip_result;
            end if;
        end if;
    end process;

    -- Выходы для SignalTap
    result_valid    <= res_valid_reg;
    mult_result     <= reg_c;
    reg_a_dbg       <= reg_a;
    reg_b_dbg       <= reg_b;
    display_reg_dbg <= display_reg;

end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity slow_generator is
    port (
        clk       : in  std_logic;
        reset     : in  std_logic;
        slow      : out std_logic;
        counter   : out std_logic_vector(3 downto 0)  -- 4 бита хватает для 0..9
    );
end slow_generator;

architecture rtl of slow_generator is
    signal cnt : unsigned(3 downto 0) := (others => '0');
begin

    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                cnt <= (others => '0');
            else
                if cnt = 9 then
                    cnt <= (others => '0');
                else
                    cnt <= cnt + 1;
                end if;
            end if;
        end if;
    end process;

    slow <= '1' when cnt = 0 else '0';
    counter <= std_logic_vector(cnt);

end rtl;