---

`timescale 1ns / 1ps
module testl_tb ;
//module testbench;
    reg       clk;
    reg       res;
    wire [7:0] counter ;

    counter_1  DUT
    (
        .res(res),
        .clk(clk),
        .counter_out(counter)
    );

    initial
    begin
            clk = 0 ;
        forever   clk = #20 ~clk ;
    end

    initial
    begin
        res = 0 ;
        #10 ;
        res = 1'b1;
        #50 ;
        res = 1'b0;
    end

endmodule