---

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity mult_controller is
    port (
        clk             : in  std_logic;
        reset_btn       : in  std_logic;
        slow            : in  std_logic;
        use_ip          : in  std_logic;
        result_valid    : out std_logic;
        bcd_0           : out integer range 0 to 9;
        bcd_1           : out integer range 0 to 9;
        bcd_2           : out integer range 0 to 9;
        bcd_3           : out integer range 0 to 9;
        bcd_4           : out integer range 0 to 9;
        -- Отладочные выходы
        reg_a_dbg       : out std_logic_vector(7 downto 0);
        reg_b_dbg       : out std_logic_vector(7 downto 0);
        reg_c_dbg       : out std_logic_vector(15 downto 0);
        display_reg_dbg : out std_logic_vector(15 downto 0)
    );
end mult_controller;

architecture rtl of mult_controller is

    -- Сигналы между модулями
    signal reg_a            : std_logic_vector(7 downto 0);
    signal reg_b            : std_logic_vector(7 downto 0);
    signal mult_ip_result   : std_logic_vector(15 downto 0);
    signal mult_logic_result: std_logic_vector(15 downto 0);
    signal selected_result  : std_logic_vector(15 downto 0);
    signal display_reg      : std_logic_vector(15 downto 0);

    -- Цепочка задержки slow
    signal slow_reg : std_logic;
    signal slow_d1  : std_logic;
    signal slow_d2  : std_logic;

begin

    -- ==========================================
    -- 1. Входная стадия: MUX + reg_a, reg_b
    -- ==========================================
    u_input : entity work.input_stage
        port map (
            clk   => clk,
            reset => reset_btn,
            slow  => slow,
            reg_a => reg_a,
            reg_b => reg_b
        );

    -- ==========================================
    -- 2. Умножители (параллельно)
    -- ==========================================
    u_mult_ip : entity work.mult_ip
        port map (
            dataa  => reg_a,
            datab  => reg_b,
            result => mult_ip_result
        );

    u_logic_mult : entity work.logic_mult
        port map (
            a      => reg_a,
            b      => reg_b,
            result => mult_logic_result
        );

    -- ==========================================
    -- 3. Мультиплексор выбора результата
    -- ==========================================
    selected_result <= mult_ip_result when use_ip = '1' else mult_logic_result;

    -- ==========================================
    -- 4. Цепочка задержки slow (3 такта)
    -- ==========================================
    process(clk)
    begin
        if rising_edge(clk) then
            slow_reg <= slow;
            slow_d1  <= slow_reg;
            slow_d2  <= slow_d1;
        end if;
    end process;

    -- ==========================================
    -- 5. Выходная стадия: reg_c, display_reg
    -- ==========================================
    u_output : entity work.output_stage
        port map (
            clk             => clk,
            reset           => reset_btn,
            slow_d1         => slow_d1,
            slow_d2         => slow_d2,
            selected_result => selected_result,
            result_valid    => result_valid,
            reg_c           => reg_c_dbg,
            display_reg     => display_reg
        );

    -- ==========================================
    -- 6. Преобразование display_reg в BCD
    -- ==========================================
    u_bcd : entity work.display_to_bcd
        port map (
            display_reg => display_reg,
            bcd_0       => bcd_0,
            bcd_1       => bcd_1,
            bcd_2       => bcd_2,
            bcd_3       => bcd_3,
            bcd_4       => bcd_4
        );

    -- Отладочные выходы
    reg_a_dbg       <= reg_a;
    reg_b_dbg       <= reg_b;
    display_reg_dbg <= display_reg;

end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity display_to_bcd is
    port (
        display_reg : in  std_logic_vector(15 downto 0);
        bcd_0       : out integer range 0 to 9;
        bcd_1       : out integer range 0 to 9;
        bcd_2       : out integer range 0 to 9;
        bcd_3       : out integer range 0 to 9;
        bcd_4       : out integer range 0 to 9
    );
end display_to_bcd;

architecture rtl of display_to_bcd is
    signal val : unsigned(15 downto 0);
begin
    val <= unsigned(display_reg);

    -- Комбинационное преобразование в 5 BCD-цифр
    bcd_0 <= to_integer((val / 10000) mod 10);
    bcd_1 <= to_integer((val / 1000)  mod 10);
    bcd_2 <= to_integer((val / 100)   mod 10);
    bcd_3 <= to_integer((val / 10)    mod 10);
    bcd_4 <= to_integer(val mod 10);

end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity output_stage is
    port (
        clk             : in  std_logic;
        reset           : in  std_logic;
        slow_d1         : in  std_logic;
        slow_d2         : in  std_logic;
        selected_result : in  std_logic_vector(15 downto 0);
        result_valid    : out std_logic;
        reg_c           : out std_logic_vector(15 downto 0);
        display_reg     : out std_logic_vector(15 downto 0)
    );
end output_stage;

architecture rtl of output_stage is
    signal reg_c_int      : std_logic_vector(15 downto 0);
    signal res_valid_reg  : std_logic;
    signal display_reg_int: std_logic_vector(15 downto 0);
begin

    -- Основной регистр reg_c (обнуляется по Варианту B)
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_c_int <= (others => '0');
                res_valid_reg <= '0';
            elsif slow_d1 = '1' then
                reg_c_int <= selected_result;
                res_valid_reg <= '1';
            else
                reg_c_int <= (others => '0');
                res_valid_reg <= '0';
            end if;
        end if;
    end process;

    -- Регистр display_reg (сбрасывается только по reset, защелкивается по slow_d2)
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                display_reg_int <= (others => '0');
            elsif slow_d2 = '1' then
                display_reg_int <= selected_result;
            end if;
        end if;
    end process;

    -- Выходы
    result_valid <= res_valid_reg;
    reg_c        <= reg_c_int;
    display_reg  <= display_reg_int;

end rtl;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity input_stage is
    port (
        clk       : in  std_logic;
        reset     : in  std_logic;
        slow      : in  std_logic;
        reg_a     : out std_logic_vector(7 downto 0);
        reg_b     : out std_logic_vector(7 downto 0)
    );
end input_stage;

architecture rtl of input_stage is
    constant NUM_A : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(12, 8));
    constant NUM_B : std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(15, 8));

    signal mux_a_out : std_logic_vector(7 downto 0);
    signal mux_b_out : std_logic_vector(7 downto 0);
begin

    -- Мультиплексоры (комбинационные)
    mux_a_out <= NUM_A when slow = '1' else (others => '0');
    mux_b_out <= NUM_B when slow = '1' else (others => '0');

    -- Регистры после мультиплексоров
    process(clk)
    begin
        if rising_edge(clk) then
            if reset = '1' then
                reg_a <= (others => '0');
                reg_b <= (others => '0');
            else
                reg_a <= mux_a_out;
                reg_b <= mux_b_out;
            end if;
        end if;
    end process;

end rtl;