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/* Enable bypass for clock sources */
DEV_SM_ClockSourceBypass(true, true);
/* Power up eFUSE */
GPC_GLOBAL->GPC_EFUSE_CTRL = 0U;
/* Restore GPC LP handshakes */
BLK_CTRL_S_AONMIX->LP_HANDSHAKE_SM = lpHsSm;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE2_SM = lpHs2Sm;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE_ELE = lpHsEle;
BLK_CTRL_S_AONMIX->LP_HANDSHAKE2_ELE = lpHs2Ele;
/* If WAKEUPMIX powered down during SUSPEND, force power up */
if (wakeupMixOff)
{
status = DEV_SM_PowerStateSet(DEV_SM_PD_WAKEUP,
DEV_SM_POWER_STATE_ON);
}
/* Check if WAKEUPMIX forced to parked level during LP compute */
if ((status == SM_ERR_SUCCESS) && restoreWakeupMixPerf)
{
/* Restore saved WAKEUPMIX performance level */
status = DEV_SM_PerfLevelSet(DEV_SM_PERF_WAKEUP,
savedWakeupMixPerf);
}
if (status == SM_ERR_SUCCESS)
{
/* If NOCMIX powered down during SUSPEND, force power up */
if (lpmSettingNoc <= sleepMode)
{
status = DEV_SM_PowerStateSet(DEV_SM_PD_NOC,
DEV_SM_POWER_STATE_ON);
}
else
{
/* Reopen DDR access if NOCMIX TRDC is not reloaded */
status = DEV_SM_RdcDdrBlock(false);
}
}
/* Check if DDR retention active */
if (ddrInRetention)
{
if (status == SM_ERR_SUCCESS)
{
/* Power up DDRMIX */
status = DEV_SM_PowerStateSet(DEV_SM_PD_DDR,
DEV_SM_POWER_STATE_ON);
}
if (status == SM_ERR_SUCCESS)
{
/* Take DDR out of retention */
status = DEV_SM_MemDdrRetentionExit();
}
}
/* Restore SM NVIC */
for (uint32_t wakeIdx = 0;
wakeIdx < GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT;
wakeIdx++)
{
NVIC->ICER[wakeIdx] = 0xFFFFFFFFU;
NVIC->ISER[wakeIdx] = nvicISER[wakeIdx];
}
/* Enable sensor */
(void) DEV_SM_SensorPowerUp(DEV_SM_SENSOR_TEMP_ANA);
/* Board-level sleep unprepare */
BOARD_SystemSleepUnprepare(s_sysSleepMode, s_sysSleepFlags);
}
}
/* Check if system did not sleep */
if (g_syslog.sysSleepRecord.wakeSource == 0U)
{
sleepExitStart = DEV_SM_Usec64Get();
/* Check the expression doesn't wrap */
if (sleepExitStart >= sleepEntryStart)
{
g_syslog.sysSleepRecord.sleepEntryUsec =
UINT64_L(sleepExitStart - sleepEntryStart);
}
else
{
/* Initialize to zero in case of wrap */
g_syslog.sysSleepRecord.sleepEntryUsec = 0U;
}
}
/* Restore GPC wake sources modified during sleep flow */
for (uint32_t cpuIdx = 0U; cpuIdx < CPU_NUM_IDX; cpuIdx++)
{
if (cpuIdx != CPU_IDX_M33P)
{
/* Restore saved GPC wake sources */
for (uint32_t wakeIdx = 0U;
wakeIdx < GPC_CPU_CTRL_CMC_IRQ_WAKEUP_MASK_COUNT;
wakeIdx++)
{
(void) CPU_IrqWakeSet(cpuIdx, wakeIdx,
cpuWakeMask[cpuIdx][wakeIdx]);
}
}
}
/* Check the expression value doesn't wrap */
if (DEV_SM_Usec64Get() >= sleepExitStart)
{
g_syslog.sysSleepRecord.sleepExitUsec =
UINT64_L(DEV_SM_Usec64Get() - sleepExitStart);
}
else
{
/* Initialize to zero in case of wrap */
g_syslog.sysSleepRecord.sleepExitUsec = 0U;
}
return status;
}
/*--------------------------------------------------------------------------*/
/* Idle the system */
/*--------------------------------------------------------------------------*/
int32_t DEV_SM_SystemIdle(void)
{
int32_t status = SM_ERR_SUCCESS;
__disable_irq();
/* Check if system sleep mode flag allows system sleep */
if ((s_sysSleepFlags & DEV_SM_SSF_SM_ACTIVE_MASK) == 0U)
{
/* Check if conditions allow system sleep */
uint32_t sysSleepStat;
if (CPU_SystemSleepStatusGet(&sysSleepStat))
{
if (sysSleepStat == CPU_SLEEP_MODE_SUSPEND)
{
status = DEV_SM_SystemSleep(CPU_SLEEP_MODE_SUSPEND);
}
/* Otherwise stay in RUN mode and enter WFI */
else
{
(void) CPU_SleepModeSet(CPU_IDX_M33P, CPU_SLEEP_MODE_RUN);
__DSB();
/* coverity[misra_c_2012_rule_1_2_violation] */
__WFI();
__ISB();
}
}
}
/* SM remains active, no system sleep */
else
{
(void) CPU_SleepModeSet(CPU_IDX_M33P, CPU_SLEEP_MODE_RUN);
__DSB();
/* coverity[misra_c_2012_rule_1_2_violation] */
__WFI();
__ISB();
}
__enable_irq();
return status;
}