---

aplay -D plughw:lt9611audio -f S16_LE -r 44100 -c 2 /tmp/test_44100.raw
Playing raw data '/tmp/test_44100.raw' : Signed 16 bit Little Endian, Rate 44100 Hz, Stereo

Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_startup(636)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_startup(642)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_startup(668) mode=0 ret=0
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_startup(674)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_startup(686)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_startup(450)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_startup(461)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611_audio_startup(1730)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_startup(468)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_startup(483)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_startup(487) ret=0!!!
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_hw_params(578)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi-audio-codec hdmi-audio-codec.6.auto: hdmi_codec_hw_params() width 32 rate 44100 channels 2
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_hw_params(591) ret=0
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: hdmi_codec_hw_params(598) ret=24
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611_hdmi_hw_params(1635) 
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611 1-003b: LT9611: Configuring Audio Input as SPDIF
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611_hdmi_hw_params(1654) sample_rate=44100
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611_hdmi_hw_params(1682) sample_width=32
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611_hdmi_hw_params(1704)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: lt9611_hdmi_hw_params(1722)
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_prepare(511) mode=0
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_prepare(598) 
Oct 27 13:14:42 imx95-19x19-lpddr5-evk kernel: fsl_xcvr_prepare(600) ret=0

static int fsl_xcvr_en_aud_pll(struct fsl_xcvr *xcvr, u32 freq)
{
	struct device *dev = &xcvr->pdev->dev;
	int ret;

	freq = xcvr->soc_data->spdif_only ? freq / 5 : freq;
	clk_disable_unprepare(xcvr->phy_clk);
	fsl_asoc_reparent_pll_clocks(dev, xcvr->phy_clk,
				     xcvr->pll8k_clk, xcvr->pll11k_clk, freq);
	ret = clk_set_rate(xcvr->phy_clk, freq);
	if (ret < 0) {
		dev_err(dev, "Error while setting AUD PLL rate: %d\n", ret);
		return ret;
	}
	ret = clk_prepare_enable(xcvr->phy_clk);
	if (ret) {
		dev_err(dev, "failed to start PHY clock: %d\n", ret);
		return ret;
	}

	if (!xcvr->soc_data->use_phy)
		return 0;
	/* Release AI interface from reset */
	ret = regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET,
			   FSL_XCVR_PHY_AI_CTRL_AI_RESETN);
	if (ret < 0) {
		dev_err(dev, "Error while setting IER0: %d\n", ret);
		return ret;
	}

	if (xcvr->mode == FSL_XCVR_MODE_EARC) { /* eARC mode */
		/* PHY: CTRL_SET: TX_DIFF_OE, PHY_EN */
		regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
				FSL_XCVR_PHY_CTRL_TSDIFF_OE |
				FSL_XCVR_PHY_CTRL_PHY_EN);
		/* PHY: CTRL2_SET: EARC_TX_MODE */
		regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL2,
				FSL_XCVR_PHY_CTRL2_EARC_TXMS);
	} else { /* SPDIF mode */
		/* PHY: CTRL_SET: TX_CLK_AUD_SS | SPDIF_EN */
		regmap_set_bits(xcvr->regmap_phy, FSL_XCVR_PHY_CTRL,
				FSL_XCVR_PHY_CTRL_TX_CLK_AUD_SS |
				FSL_XCVR_PHY_CTRL_SPDIF_EN);
	}

	dev_dbg(dev, "PLL Fexp: %u\n", freq);

	return 0;
}

static const struct fsl_xcvr_soc_data fsl_xcvr_imx95_data = {
	.fw_name = "imx/xcvr/xcvr-imx95.bin",
	.spdif_only = true,
	.use_phy = true,
	.use_edma = true,
	.pll_ver = PLL_MX95,
};